P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 9/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Architecture

The P-tile Avalon® -ST IP for PCI Express* consists of the following major sub-blocks:
  • Four PCIe* cores (one x16 core, one x8 core and two x4 cores)
  • Embedded Multi-die Interconnect Bridge (EMIB)
  • Soft logic blocks in the FPGA fabric to implement functions such as VirtIO, etc.
Figure 1. P-tile Avalon® -ST IP for PCI Express* top-level block diagram
Note: Each core in the PCIe Hard IP implements its own Data Link Layer and Transaction Layer.

The four cores in the PCIe Hard IP can be configured to support the following topologies:

Table 9.  Configuration Modes Supported by the P-tile Avalon-ST IP for PCI Express
Configuration Mode Native IP Mode Endpoint (EP) / Root Port (RP) / TLP Bypass (BP) Active Cores
Configuration Mode 0 Gen3 x16 or Gen4 x16 EP/RP/BP x16
Configuration Mode 1 Gen3 x8/Gen3 x8 or Gen4 x8/Gen4 x8 EP/BP x16, x8
Configuration Mode 2 Gen3 x4/Gen3 x4/Gen3 x4/Gen3 x4 or Gen4 x4/Gen4 x4/Gen4 x4/Gen4 x4 RP/BP x16, x8, x4_0, x4_1
Configuration Mode 3 Gen3 x8 or Gen4 x8 EP x16

In Configuration Mode 0, only the x16 core is active, and it operates in 1x16 Hard IP mode (in either Gen3 or Gen4).

In Configuration Mode 1, the x16 core and x8 core are active, and they operate as two Gen3 x8 cores or two Gen4 x8 cores.
Note: When you use only one of the x8 bifurcated ports, you must ensure that the other bifurcated port's lanes are not physically connected. If you connect both x8 bifurcated ports to a x16 Root Port/Switch device, it is non-deterministic which x8 port will be trained.

In Configuration Mode 2, all four cores (x16, x8, x4_0, x4_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores.

In Configuration Mode 3, the x16 core is active, and it operates in 1x8 Hard IP mode (in either Gen3 or Gen4).

Note: When you enable only one x8 Port0, make sure to select Gen3 or Gen4 1x8 in the Hard IP Mode option and physically connect Port0's lanes 0-7.

Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes. For more details, refer to the Overview section of the Interfaces chapter.