P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.3.5.9. BFM Configuration Procedures

All Verilog HDL arguments are type integer and are input‑only unless specified otherwise.