AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

ID 683045
Date 10/30/2018
Public
Document Table of Contents

1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System

After adding the Avalon® -ST Single Clock FIFO component to board.qsys, connect the component's exported signals by generating HDL.
  1. Save the board.qsys system.
  2. Click Close.
  3. From the Generate menu in Platform Designer, select Generate HDL. Alternatively, click Generate HDL in the lower right corner of the Platform Designer window.
  4. Click Generate.
  5. Click Close when HDL generation is completed. Ignore any warnings that might appear.