F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/04/2021
Public

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8.1.2. FEC and Transceiver Control and Status Registers

Lane segments organize the FEC and Transceivers registers. Each lane segment includes set of registers, replicated multiple times depending on the number of Ethernet fractures or FEC lanes required for a specific Ethernet mode.
Table 64.  FEC/Transceiver Lane Segment Base Address per Ethernet ModeThe table describes the layout and a base address for each segment.
Ethernet Mode FEC/Transceiver Lane Segment eth_reconfig Base Address
25GE Segment 0 0x6000
50GE Segment 0 0x6200
Segment 1 0x6400
100GE Segment 0 0x6600
Segment 1 0x6800
Segment 2 0x6A00
Segment 3 0x6C00
200GE Segment 0 0x6E00
Segment 1 0x7000
Segment 2 0x7200
Segment 3 0x7400
Segment 4 0x7600
Segment 5 0x7800
Segment 6 0x7A00
Segment 7 0x7C00
400GE Segment 0 0x7E00
Segment 1 0x8000
Segment 2 0x8200
Segment 3 0x8400
Segment 4 0x8600
Segment 5 0x8800
Segment 6 0x8A00
Segment 7 0x8C00
Segment 8 0x8E00
Segment 9 0x9000
Segment 10 0x9200
Segment 11 0x9400
Segment 12 0x9600
Segment 13 0x9800
Segment 14 0x9A00
Segment 15 0x9C00

The offset address describes the registers within one lane segment. The offset address combined with the lane segment base address creates the registers eth_reconfig address.

Table 65.  FEC/Transceiver Lane Segment Offset Address RangeThe table displays the offset address space for a specific lane segment.
FEC/Transceiver Interface Function FEC/Transceiver Interface Lane Segment Offset Address Range
Transceiver Interface Control 0x000 - 0x0BC
FEC Configuration 0x0C0 - 0x0FC
Transceiver Status 0x100 - 0x13C
FEC Status 0x140 - 0x1FC

The lane segment in a given Ethernet mode does not support all FEC control and stats registers. Some registers are only valid in segment 0 or in every forth segment.