8.1.1. Ethernet Hard IP Core CSRs
The Ethernet Hard IP CSRs consist of the MAC, PCS, and PTP registers implemented in the hardened Ethernet core on the F-Tile. These CSRs are set at device configuration time and cannot be reset back to their default values other than by re-writing.
The register addresses in the EHIP consist of a base address that is set based on Ethernet mode, and an offset from that address which is the same for all Ethernet modes. Below table displays all eth_reconfig base addresses. For example, the same registers from 0x1000-0x1FFC for a 25GE port are located at 0x2000-0x2FFC for a 50GE port, etc. All register addresses in the following sections are Offset Addresses and must be combined with the appropriate Base Address for the current Ethernet mode.
|eth_reconfig Base Address
|Ethernet Hard IP Function
|Ethernet Hard IP Offset Address Range