F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/04/2021
Public

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9.1.5. Clocks and Resets

Table 68.  Clock and Reset Ports
Name Description
i_clk Clock source with 100 MHz - 250 MHz frequency.
i_reset Active high reset, synchronous to i_clk clock.
Table 69.   Avalon® Memory-Mapped Interface PortsThe interface signals are clocked by the i_clk clock.
Name Width Description
i_kr_reconfig_addr[11:0] 12 Address bus for auto-negotiation and link training control and status registers (AN/LT CSRs).
  • Bits [11:8]: Port number
  • [7:0]: CSR space for each port
i_kr_reconfig_read 1 Read enable for AN/LT CSRs.
i_kr_reconfig_write 1 Write enable for AN/LT CSRs.
i_kr_reconfig_byte_en[3:0] 4 AN/LT byte enable signal for writing data.
i_kr_reconfig_writedata[31:0] 32 Write data for AN/LT CSRs.
o_kr_reconfig_readdata[31:0] 32 Read data from AN/LT CSRs.
o_kr_reconfig_readdata_valid 1 Valid signal for AN/LT CSRs read data. When asserted, the register is valid.
o_kr_reconfig_waitrequest 1 Indicates that the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low.
Table 70.  Base IP Ports Connection
Name Width Description
anlt_link [NUMPORTS_GUI-1:0] Used to connect to NUMPORTS_GUI Ethernet IP Instances. You must connect the port to the anlt_link port of the F-Tile Ethernet Intel® FPGA Hard IP.
Note: This is a virtual wire that carries no signal information used by the Intel® Quartus® Prime Tile Logic Generation flow to correctly connect the AN/LT IP to the Ethernet IP.