F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/04/2021
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7.8. PCS Mode RX Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Table 47.  Signals of the MII RX Client InterfaceAll interface signals are clocked by the RX clock. The signal names are standard Avalon® streaming interface signals.

Signal Name

Width

Description

o_rx_mii_d[1023:0]

o_rx_mii_d[511:0]

o_rx_mii_d[255:0]

o_rx_mii_d[127:0]

o_rx_mii_d[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (40GE/50GE)

64 bits(10GE/25GE)

RX MII data. Data is in MII encoding. o_rx_mii_d[7:0] holds the first byte the IP core received on the Ethernet link. o_rx_mii_d[0] holds the first bit the IP core received on the Ethernet link.

When RX MII valid signal has the value of 0 or the RX valid alignment marker signal has the value of 1, the value on this signal is invalid.

o_rx_mii_c[127:0]

o_rx_mii_c[63:0]

o_rx_mii_c[31:0]

o_rx_mii_c[15:0]

o_rx_mii_c[7:0]

128 bits (400GE)

64 bits (200GE)

32 bits (100GE)

16 bits (40GE/50GE)

8 bits(10GE/40GE)

RX MII control bits. Each bit corresponds to a byte of RX MII data. o_rx_mii_c[0] corresponds to o_rx_mii_d[7:0], o_rx_mii_c[1] corresponds to o_rx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

o_rx_mii_valid

1 bit Indicates that the RX MII data, RX MII control bits, and the RX valid alignment marker signals are valid.

o_rx_mii_am_valid

1 bit Indicates the IP core received a valid alignment marker on the Ethernet link.

When the RX MII valid signal has the value of 0, the value on this signal is invalid. The value of the RX MII valid signal may fall while the IP core is asserting this signal.

Figure 39. Receiving Data Using the PCS Mode RX Interface

The figure above shows how to read packets from the RX PCS using the PCS mode RX interface.

  • The packets are MII encoded.
    • Each byte in o_rx_mii_d has a corresponding bit in o_rx_mii_c that indicates whether the byte is a control byte or a data byte; for example, o_rx_mii_c[2] is the control bit for o_rx_mii_d[23:16].
  • The data is only valid when o_rx_mii_valid is high. The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low.
  • The byte order for the PCS mode RX interface is opposite of the byte order for the MAC segmented client interface. Bytes flow from LSB to MSB; the first byte that the core receives is o_rx_mii_d[7:0].
  • The bit order for the PCS mode RX interface is the same as the bit order of the MAC segmented client interface. The first bit that the core receives is o_rx_mii_d[0].
Note: The PCS mode RX interface is not SOP aligned. New packets can begin on any byte position that is divisible by 8 (PCS data is transferred in 8-byte blocks).
Table 48.  Reading a Start Packet Block with Preamble from a PCS Mode TX Interface
MII Data MII Control Ethernet Packet Byte
o_rx_mii_d[7:0] 0xFB o_rx_mii_c[0] 1 Start of Packet
o_rx_mii_d[15:8] 0x55 o_rx_mii_c[1] 0 Preamble
o_rx_mii_d[23:16] 0x55 o_rx_mii_c[2] 0 Preamble
o_rx_mii_d[31:24] 0x55 o_rx_mii_c[3] 0 Preamble
o_rx_mii_d[39:32] 0x55 o_rx_mii_c[4] 0 Preamble
o_rx_mii_d[47:40] 0x55 o_rx_mii_c[5] 0 Preamble
o_rx_mii_d[55:48] 0x55 o_rx_mii_c[6] 0 Preamble
o_rx_mii_d[63:56] 0xD5 o_rx_mii_c[7] 0 SFD
Figure 40. Receiving Alignment Markers

o_rx_mii_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_mii_valid. When o_rx_mii_valid is low, o_rx_mii_am_valid is not valid.

The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low. This is because alignment markers are not part of the 64b/66b encoding, and do not have an MII equivalent.