F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 10/04/2021
Public

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5.6. Custom Cadence

You can use custom cadence to ensure that the TX PMA interface FIFO doesn’t overflow due to the over clocking of the datapath. You must use the custom cadence in the following 2 scenarios:
  • When the reference clock for TX PMA and the reference clock for system PLL are different. Although, system PLL frequency is configured to be same as PMA parallel frequency, there might be PPM differences between TX PMA parallel clock frequency and system PLL frequency.
  • When the system PLL frequency is more than the PMA parallel clock frequency. This non-standard system PLL frequency may require when several interfaces share the same system clock ( some interfaces need to run at over-clocked system PLL frequency greater than PMA parallel clock frequency). This scenario may occur due to a limited number of system PLLs or when dynamic reconfiguration is enabled.

If your interface requires custom cadence, you must enable custom cadence. To enable custom cadence, select System PLL frequency IP parameter to Custom and input your required custom system PLL frequency.

When System PLL frequency IP parameter is set to Custom, the IP internally includes a custom cadence controller.

If you require an external custom cadence controller instead, you must enable it by selecting External Custom Cadence Controller IP parameter. When selected, this option enables the external custom cadence controller and i_custom_cadence input port becomes available in the IP port list. You must drive the i_custom_cadence input port producing a steady data valid cadence.

In multiple IP instance designs, you may use the external custom cadence controller option to share the logic with multiple IPs and reduce the resource utilization.

Table 26.  Custom Cadence Use Cases
Abbreviations:
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL91: IEEE 802.3 RS(528,514) (CL91)
  • CL134: IEEE 802.3 RS(544,514) (CL134)
  • ETC: Ethernet Technology Consortium ETC RS(272, 258)
  • MAC AvST: MAC Avalon® ST
  • MAC Seg: MAC Segmented
Configuration System PLL frequency (in MHz) Use Case Custom Cadence Controller Selection
NRZ modes
  • with FEC mode:
    • None
    • CL74
    • CL91
  • with client interface:
    • MAC Seg
    • MAC AvST
830.078125
  • If system PLL is shared with FEC mode configuration CL134 or ETC and system PLL reference clock and PMA reference clock sources are same and use the same clock frequency (0 ppm).
  • If system PLL reference clock and PMA reference clock sources are different, enable Custom system PLL Frequency and set the input to 830.078125 MHz.

The IP enables internal custom cadence controller logic when 830.078125 MHz is selected instead of typical 805.6640625 MHz.

PCS

OTN

FlexE

805.6640625

or

830.078125

  • If system PLL reference clock and PMA reference clock sources are same and use the same clock frequency (0 ppm).
  • If system PLL reference clock and PMA reference clock sources are different, enable Custom system PLL Frequency and set the input to 805.6640625 or 830.078125 MHz.

The IP enables internal custom cadence controller logic when 830.078125 or 805.6640625 MHz.

Any variant with client interface:
  • MAC Seg
  • MAC AvST
  • MII PCS only
  • PCS66 OTN
  • PCS66 FlexE
Custom PLL
  • Requires a non-standard system PLL frequency, for example 900 MHz.
  • System PLL reference clock and PMA reference clock sources are different.
The IP enables internal custom cadence controller when the external custom cadence controller is disabled.

When the external custom cadence controller is enabled, you must drive the i_custom_cadence port.

Table 27.  Various Custom Cadence Scenarios for 25GE-1 with IEEE 802.3 RS(528,514) (CL91) FEC ModeThe example assumes system PLL frequency of 805.6640625 MHz.
Client Interface System PLL Frequency (in MHz) PMA/System PLL Reference Clock Source Custom Cadence Required Custom Cadence Controller Client Interface Frequency FIFO Requirement
MAC Avalon® ST 805.6640625 Same No Same as system PLL frequency/2

(402.83203125 MHz)

No
MAC Avalon® ST 805.6640625 Same No Different as system PLL frequency/2

(For example, 390.625 MHz)

Enable asynchronous adapter clocks parameter is On
MAC Avalon® ST Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

402.83203125 MHz)

No
MAC Avalon® ST Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example, 390.625 MHz)

Enable asynchronous adapter clocks parameter is On 14
MAC Avalon® ST 830.078125 Same Yes Internal Same as system PLL frequency/2

(415.078125 MHz)

No
MAC Avalon® ST 830.078125 Same Yes Internal Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

Enable asynchronous adapter clocks parameter is On
MAC Avalon® ST Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

415.078125 MHz/450 MHz)

No
MAC Avalon® ST Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

Enable asynchronous adapter clocks parameter is On14
MAC segmented 805.6640625 Same No Same as system PLL frequency/2

(402.83203125 MHz)

No
MAC segmented 805.6640625 Same No Different as system PLL frequency/2

(For example, 390.625 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

402.83203125 MHz)

No
MAC segmented Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example, 390.625 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented 830.078125 Same Yes Internal Same as system PLL frequency/2

(415.078125 MHz)

No
MAC segmented 830.078125 Same Yes Internal Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

415.078125 MHz/450 MHz)

No
MAC segmented Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
14 When using multiple IP instances, if both Enable asynchronous adapter clocks and External Custom Cadence Controller are enabled, you must generate each IP's i_custom_cadence signal using corresponding o_clk_pll clock.