Intel® Stratix® 10 Hard Processor System Remote System Update User Guide

ID 683021
Date 2/23/2024
Document Table of Contents

1.2. System Components

This section describes the system components in the following figure and table.
Figure 2. System ComponentsThe following figure describes the typical components of an Intel® Stratix® 10 SoC based system using RSU.

The bitstream is stored in the configuration flash device (QSPI) connected to the SDM pins. The HPS software is typically stored in a mass storage flash device (SD/eMMC/NAND) connected to the HPS pins but can also be stored in the flash device connected to the SDM pins.

Table 1.  System Components
Component Description
FPGA Configuration Data When using FPGA first mode, this component of the bitstream contains the full FPGA and I/O configuration data. When using HPS first mode, it contains just the HPS and HPS EMIF I/Os.
SDM Firmware

Firmware for the Secure Device Manager

Provides commands for managing RSU. These commands are not directly accessible to you. Instead both U-Boot and Linux* offer services for accessing the functionality offered by the SDM commands indirectly.

U-Boot SPL

The HPS First Stage Bootloader

Initializes hardware and loads the HPS Second Stage Bootloader.


Arm Trusted Firmware

Provides secure services to U-Boot and Linux through SMC (Secure Monitor Call)5


HPS Second Stage Bootloader:

  • Loads and boots the operating system
  • Provides RSU APIs and command line capabilities.
  • Uses ATF SMC calls to indirectly access the SDM services.
Linux* Drivers

Intel® RSU driver uses the functionality provided by U-Boot SMC and makes services available to applications running on Linux*.


Linux* user space library providing APIs for managing RSU.

RSU Client

Linux* sample application which uses LIBRSU for managing RSU.

Intel® provides an RSU solution that focuses on the reliable update of the components that are part of the configuration bitstream, and are located in SDM flash. It is your responsibility to devise a scheme for the reliable update of the rest of the system components.

For information about version compatibility requirements of various system components, refer to the Version Compatibility Considerations section.

5 On Cortex*-A53, there are four execution levels: EL0-Application, EL1-OS, EL2-Hypervisor, and EL3-Secure Monitor. Interacting with SDM is only allowed for software running at EL3. ATF runs at EL3, U-Boot and Linux* run at EL1. For U-Boot and Linux* to communicate with the SDM, they have to issue an SMC trap to a handler left resident by ATF. Then that handler runs at EL3 and is able to communicate with the SDM.