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1.1. SDI II Intel® FPGA IP v19.5.0
1.2. SDI II Intel® FPGA IP v19.4.0
1.3. SDI II Intel® FPGA IP v19.3.2
1.4. SDI II Intel® FPGA IP v19.3.0
1.5. SDI II Intel® FPGA IP v19.2.1
1.6. SDI II Intel® FPGA IP v19.2
1.7. SDI II Intel® FPGA IP v19.1
1.8. SDI II Intel® FPGA IP v18.1 Update 2
1.9. SDI II Intel® FPGA IP v18.1 Update 1
1.10. SDI II Intel® FPGA IP v18.1
1.11. SDI II Intel® FPGA IP v18.0
1.12. Intel FPGA SDI II IP Core v17.1
1.13. SDI II IP Core v17.0
1.14. SDI II IP Core v16.1
1.15. SDI II IP Core v16.0
1.16. SDI II IP Core v15.1
1.17. SDI II IP Core v15.0
1.18. SDI II IP Core v14.1
1.19. Serial Digital Interface (SDI) II User Guide Archives
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1.18. SDI II IP Core v14.1
| Description | Impact |
|---|---|
| The run_sim script for each simulator is now located in its respective folder. | - |
| rx_format signal now reports video transport format instead of picture format. The signal reports 3G Level A RGB or YCbCr 4:4:4 format. | If you update to the Quartus II software version 14.1, you must update your SDI II IP core to incorporate this fix. |
Changed the names of the following parameters:
|
- |