Serial Digital Interface (SDI) II Intel® FPGA IP Release Notes

ID 683016
Date 4/09/2024

1.16. SDI II IP Core v15.1

Table 16.  v15.1 November 2015
Description Impact
Redefined the rx_format signal. Each stream of 6G-SDI and 12G-SDI interfaces reports its own detected rx format. For example, when receiving 2160p60 in 12G-SDI, all 4 streams are expected to report 1080p60. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added new interface signals for Arria V, Cyclone V, and Stratix V devices:
  • rx_trs_in
  • pll_powerdown_in
  • pll_ powerdown_out
Added new reconfiguration management parameters for Arria 10 devices:
Fixed jitter tolerance reduction issue when receiving SD-SDI video standards.
Updated the sdc constraint for the dual-clock FIFO (DCFIFO) component instantiated in the core.