Serial Digital Interface (SDI) II Intel® FPGA IP Release Notes

ID 683016
Date 10/02/2023
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1.10. SDI II Intel® FPGA IP v18.0

Table 9.  v18.0 May 2018
Description Impact
Renamed Intel FPGA SDI II IP to SDI II Intel® FPGA IP as part of standardizing and rebranding exercise.
Added support for Xcelium* Parallel simulator. These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Added a new parameter, Rx core clock (rx_coreclk) frequency. This parameter is available only when you select Multi rate (up to 12G) and Receiver or Bidirectional direction in the Intel® Quartus® Prime Pro Edition software.

Updated the rx_coreclk_is_ntsc_paln signal to include 297.0 MHz and 296.70 MHz options.
Added Parallel loopback without external VCXO option for Intel® Stratix® 10 design example.
Added the following files:
  • pid_controller.v
  • rcfg_pll_frac.v
  • modelsim_files.tcl
  • ncsim_files.tcl
  • riviera_files.tcl
  • vcs_files.tcl
  • vcsmx_files.tcl
  • xcelium_files.tcl
  • tb_ln_check.v
  • cds.lib
  • hdl.var
  • xcelium_setup.sh
  • xcelium_sim.sh
Added final support for Intel® Cyclone® 10 GX devices. The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software.
Added new design examples for Intel® Cyclone® 10 GX devices in version 17.1.1 release. Refer to the SDI II Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information.
Table 10.  Design Files Required for IP Upgrade

The implementation of the IP on hardware requires additional components specific to the device targeted.

These additional components, such as Native PHY, TX PLL, reconfiguration controller, are not included as part of the Intel® Quartus® Prime IP Upgrade flow. Upgrading an IP core would require the inclusion of these files generated as part of the IP design example.

Design Example Required Files
Intel® Arria® 10
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
Intel® Cyclone® 10 GX
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
Intel® Stratix® 10
  • sdi_ii_a10_demo.v
  • sdi_ii_a10_demo.sdc
  • edge_detector.sv
  • clock_heartbeat.sv
  • a10_reconfig_arbiter.sv
  • Files inside the <vid_pattgen> folder
  • Files inside <loopback> folder
  • Files inside <du>, or <rx> and <tx> folders
  • Files inside <mr_phy_adapter> folder