Developer Guide

Intel oneAPI FPGA Handbook

ID 785441
Date 2/07/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Timing Failures

If your FPGA compile fails to meet timing requirements, the Intel® oneAPI DPC++/C++ Compiler deletes the generated FPGA image, prints an error message, and returns an error code. This means that the generated FPGA image did not meet all timing constraints. The best solution is usually to recompile with a different seed (see -Xsseed=<value> in Other SYCL* FPGA Flags Supported by the Compiler). However, some rare designs where the FPGA is extremely full might require sweeping several seeds to find one that passes the timing checks. If your design has chronic timing failures and you cannot resolve with seed sweeps, consult your BSP vendor.

When a timing failure happens, the compiler generates a *.failing_clocks.rpt file. The path to this file and file name are dependent on your BSP. This .rpt file lists which clocks in your design had failing paths and the magnitude of failures.