Developer Guide

Intel oneAPI FPGA Handbook

ID 785441
Date 2/07/2024
Public

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Bottlenecks Viewer

The Bottlenecks viewer, when used with the Loop Analysis and Schedule Viewer, provides information about the throughput bottleneck(s) in your design. This viewer lists all loops that result in a bottleneck for the currently selected system, kernel, or task. You can select these loops to view more details about the bottleneck in the Details pane. For more information about the concept of bottlenecks, refer to Remove Loop Bottlenecks.

The Bottlenecks viewer identifies the following categories of bottlenecks:

  • FMAX reduced, II increased, or both
  • Compiler applied bottlenecks (private copies set to 1 on local memory)
  • Bottlenecks due to pragmas or attributes you apply on a loop
  • Concurrency limiter bottlenecks

For example, consider a simple loop with memory dependency from the Triangular Loops example:

for (int y = x + 1; y < n; y++) {
  local_buf[y] = local_buf[y] + SomethingComplicated(local_buf[x]);
}

In the Loop Analysis viewer, this loop is identified as having an II of 30. When you select this loop in the Loop Analysis report, you can find the following message in the Details pane:

Compiler failed to schedule this loop with smaller II due to memory dependency:
     From: Load Operation (triangular_loop.cpp: 78)
     To: Store Operation (triangular_loop.cpp: 78)
Compiler failed to schedule this loop with smaller II due to memory dependency:
     From: Load Operation (triangular_loop.cpp: 78)

In the Bottlenecks viewer, you can then select the loop to display more information in the Details pane, which you can use to investigate why and what caused this bottleneck. For additional information about the bottlenecks, refer to System Viewer and Schedule Viewer reports. The System Viewer provides information about the isolated failing path and bottleneck type. The Schedule Viewer displays the bottleneck path for the variable.