Cyclone® 10 LP FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Cyclone® 10 LP

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Device Datasheet

Cyclone® 10 LP Device Design Guidelines

Cyclone® 10 LP Device Overview

Cyclone® 10 LP Device Family Pin Connection Guidelines

LVDS SERDES Transmitter / Receiver IP Cores User Guide

FPGA Parallel Flash Loader IP Core User Guide

Altera® ASMI Parallel II IP Core User Guide

Altera® ASMI Parallel IP Core User Guide

Altera® Remote Update IP Core User Guide

AN 447: Interfacing FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

AN 496: Using the Internal Oscillator IP Core

AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families

AN 731: Simultaneous Switching Noise Guidelines for Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software
View all Show less
Design Examples
Cyclone® 10 LP

Cyclone® 10 LP Design Examples on Design Store
View all Show less

2. Interface Protocol

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Ethernet

FPGA IP for Ethernet - Support Center
View all Show less
User Guides
PCI Express*

FPGA IP for PCI Express – Support Center
View all Show less
User Guides
Digital Signal Processing (DSP)

FPGA CORDIC IP Core User Guide

BCH IP Core User Guide

FFT IP Core User Guide

FIR II IP Core User Guide

Viterbi IP Core User Guide

Turbo IP Core User Guide

Floating-Point IP Cores User Guide

High-Speed Reed-Solomon IP Core User Guide

Reed-Solomon II IP Core User Guide

Random Number Generator IP Core User Guide
View all Show less
Training and Videos
External Memory Interface

Guide for New External Memory Interface (EMIF) Spec Estimator
View all Show less
FPGA Wiki
External Memory Interface

Board Skew Parameter Tool Guide

Automated EMIF Layout Checks
View all Show less

3. Design Planning

Documentation

Training and Videos

Fast & Easy I/O System Design with BluePrint
View all Show less

4. Design Entry

Documentation

The Quartus® Prime Software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

User Guides / Device Overview / Device Datasheet / White Paper

Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis
View all Show less

Design Examples

Platform Designer Design Examples

Platform Designer Pro Tutorial Design Example for Arria® 10 FPGA (.zip)

Platform Designer Tutorial Design Example for Arria® 10 FPGA (.zip)

Platform Designer Tutorial Design Example (.zip)

Quartus® Design Examples
View all Show less

Training and Videos

Using the Quartus® Prime Software: An Introduction

Introduction to Verilog HDL

Verilog HDL Basics

Advanced Verilog HDL Design Techniques

SystemVerilog with the Quartus® II Software

VHDL Basics

Introduction to Platform Designer

Platform Designer in the Quartus® Prime Pro Edition Software

Creating a System Design with Platform Designer: Getting Started

Using Spectra-Q Synthesis in the Quartus® Prime Software
View all Show less

Software Downloads

Download center for all versions of the Quartus® Prime software
View all Show less

5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Quartus® Prime Standard Edition User Guide: Third-party Simulation

Simulating the a8237 Model with the Visual IP Software

Avalon® Verification IP Suite User Guide

FPGA Software Installation and Licensing

Simulating the a8251 Model with the Visual IP Software

Simulating the a8259 Model with the Visual IP Software

Simulating the Reed-Solomon Model with the Visual IP Software

Simulating the Turbo Encoder/Decoder Model with the Visual IP Software

AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix® 10 Devices

AN 720: Simulating the ASMI Block in Your Design

AN 351: Simulating Nios® II Processor Designs

AN 508: Cyclone® III Simultaneous Switching Noise (SSN) Design Guidelines

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

Simulating Altera® Devices with IBIS Models

Simulating FPGA Designs
View all Show less

Design Examples

Avalon® Verification IP Suite Design Example
View all Show less

Training and Videos

Advanced System Design Using Qsys: System Verification with System Console

Advanced System Design Using Qsys: Component & System Simulation

Design Software Online Demonstration

Avalon® Verification Suite

Verifying Memory Interfaces IP in Arria® 10 Devices
View all Show less

FPGA Wiki

Simulating Designs with Lower-Level Qsys Systems

Arria® 10 EMIF Simulation Guidance

DDR4 Simulation Guidelines

Simpler Chaining DMA Testbench Example
View all Show less

Software Downloads

Quartus® Software
View all Show less

6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization

Cyclone® 10 LP Device Design Guidelines
View all Show less

Training and Videos

Design Block Reuse in the Quartus® Prime Pro Software

Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Design Partitioning

Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Introduction

Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Timing Closure & Tips
View all Show less

7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Timing Analysis Overview

Quartus® II Scripting Reference Manual

SDC and TimeQuest API Reference Manual

Quartus® Prime Timing Analyzer Cookbook

AN 366: Understanding I/O Output Timing for Altera® Devices

AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 433: Constraining and Analyzing Source-Synchronous Interfaces

AN 775: I/O Timing Information Generation Guidelines
View all Show less

Design Examples

Timing Analyzer Design Examples
View all Show less

Training and Videos

Getting Started with the TimeQuest Timing Analyzer
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
FPGA Timing Closure: Lecture
FPGA Timing Closure: Hands-On Lab
View all Show less

FPGA Wiki

Source Synchronous Interfaces between FPGAs

Source Synchronous Analysis with TimeQuest

Constraining Edge Aligned Source Synch input interfaces in TimeQuest

Constraining Center Aligned Source Synchronous Input Interfaces in TimeQuest

DDR Timing with TimeQuest
View all Show less

8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes

Design Debugging Using In-System Sources and Probes

FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide

FPGA-Adaptive Software Debug and Performance Analysis

System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug

ByteBlaster II Download Cable User Guide

FPGA USB Download Cable User Guide

FPGA Download Cable II User Guide

EthernetBlaster Communications Cable User Guide

BSDL Support

AN 827: Unified Tool for Generating Programming Files

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files

AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer

AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC

AN 541: SerialLite II Hardware Debugging Guide

AN 543: Debugging Nios II Software Using the Lauterbach Debugger

AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench

AN 624: Debugging with System Console over TCP/IP
View all Show less

Training and Videos

Debugging JTAG Chain Integrity

On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices

SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

Quartus® Software Debug Tools

JTAG Chain Debugger Tool

Quick Signal Tapping with SignalProbe in the Altera Quartus® II Software
View all Show less

FPGA Wiki

Debug Apps

Development Boards and Kits

DisplayPort MegaCore Debug Checklist

System Console

Low Latency Ethernet 10G MAC Debug Checklist

SDI II MegaCore Debug Checklist

10Gbps Ethernet MAC Debug Checklist

Arria® 10 EMIF Debug GUI

Arria® 10 Debugging Multiple EMIFs
View all Show less

Software Downloads

FPGA Programming Software

Cable and Adapter Drivers Information

Quartus® Prime Software Stand-Alone Programmer
View all Show less