Gate-Level Simulation with ModelSim-Altera Simulator(Verilog HDL)

You can use this design example to learn how to perform gate-level timing simulations of your design implemented in Stratix® II devices with the Mentor Graphics® ModelSim®-Altera® simulator. In this example you will:

  • Load an existing project in the Quartus® II software
  • Set up a Quartus II project to generate the required files for simulation
  • Compile your design in the Quartus II software to generate a gate-level netlist
  • Understand the outputs generated for gate-level timing simulation
  • Run the simulation with the scripts provided and understand the results

The design is created using Verilog HDL and consists of a top-level module (multiplier block), a phase-locked loop (PLL) megafunction, an alt_mult megafunction, an lpm_ram megafunction, and a testbench. All the device libraries required for this gate-level simulation example come pre-compiled with the ModelSim-Altera software.

Note: This example was developed using Quartus II software version 9.0 SP2 running on a Windows XP SP2 machine and Mentor Graphics ModelSim-Altera software version 6.4a running on the same host.

Download the multiplier_verilog_AE.qar design example.

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Using This Design Example

Follow these steps to use the design example.

  1. Invoke the Quartus II software
  2. Go to Project, select Restore Archived Project.
  3. In the Archive file name box, type the name of the multiplier_verilog_AE.qar file or click Browse to select the above .qar file.
  4. In the Destination folder box, specify the directory path in which you will restore the contents of the file, or browse to a directory that you wish to save.
    Note: You can also double click on the .qar file and the Quartus II software will automatically open and perform the archive file process.
  5. On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named multiplier.vo (for use with the ModelSim-Altera simulator tool) in <project_dir>/simulation/modelsim. The SDF Output File (multiplier_v.sdo) for annotating the delays in the gate-level timing simulation file is also generated at the same location.

To run simulation, use one of the following methods:

Method 1: Running the Quartus II NativeLink Software

Go to the Tools menu, under EDA Simulation Tool, click Run EDA Gate Level Simulation.

Note: For more information, please go to How to use Quartus II NativeLink Feature web page (shows you the setting for the NativeLink feature).

Method 2: Running the Modelsim SE/PE Software

  1. Invoke the ModelSim SE/PE software.
  2. Go to File menu, navigate to the following directory: <project_dir>/simulation/modelsim.
  3. Run the multiplier_run_msim_gate_verilog script provided by this design example. To run this script, type do multiplier_run_msim_gate_verilog.do at the command line, and then press Enter.

The ModelSim-Altera simulator compiles the testbench and the netlist (multiplier.vo), annotates the SDF data (in multiplier_v.sdo), and runs the simulation for the specified time. A waveform window within the ModelSim-Altera simulator is invoked that shows the expected and actual results of the multiplier. The expected and actual results are also checked in the testbench, and messages that show whether or not the results match are displayed in the simulator’s console window. The data output of the multiplier module changes with a delay after the clock edge because the SDF data is annotated in the gate-level timing simulation.

Note: For more information about how to manually perform simulation, please go to the Quick Step on how to manually run simulation web page.

For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim and QuestaSim Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook.

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These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.