The list below contains design examples demonstrating gate-level timing simulation of Intel® devices. Gate-level timing simulations are performed with Mentor Graphics* ModelSim* software to ensure that the post-synthesized or post-fit netlist passes the functional specifications.
Stratix® II GX Post-Fit Timing Simulation
Stratix II Post-Fit Timing Simulation
Stratix IV GX Post-Fit Timing Simulation
Design Examples Disclaimer
These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.