DDR5 and DDR4 EMIF FPGA IP
DDR5 and DDR4 offer higher performance, density and lower power and more control features compared to DDR3. Our FPGA DDR5 and DDR4 EMIF IP offers solutions for high computing memory needs for client and data center systems.
Read Agilex™ 5 FPGA EMIF user guide ›
Read Agilex™ 7 FPGA M-Series EMIF IP user guide ›
Read Agilex™ 7 FPGA F-Series and I-Series EMIF IP user guide ›
DDR5 and DDR4 EMIF FPGA IP
Hardening the Controller and PHY Offers Several Advantages which Include:
- Shorter development cycles and faster time to market due to pre-closed timing
- More FPGA fabric logic resources available for user application
- Improved fmax, efficiency and latency
- Low power solution
Utilize these advantages on Agilex™ 5 devices, Agilex™ 7 devices, Stratix® 10 devices, and Arria® 10 FPGAs across various applications: industrial, wireless/wireline, broadcast, medical, retail, test measurement, and more.
EMIF Protocols & Features
Feature |
Agilex™ 5 FPGAs |
Agilex™ 7 FPGA M-Series |
Agilex™ 7 FPGA I- and F- Series |
Stratix® 10 FPGA |
---|---|---|---|---|
DDR5 |
Yes |
Yes |
No |
No |
LPDDR5 |
Yes |
Yes |
No |
No |
DDR4 |
Yes |
Yes |
Yes |
Yes |
LPDDR4 |
Yes |
No |
No |
No |
QDRIV |
No |
No |
Yes |
Yes |
Max Interface Width |
X72(DDR4) |
X80(DDR5) |
X72(DDR4) |
X72(DDR4) |
Maximum Interface Rate |
4667 Mbps (LPDDR5) |
5600 Mbps (DDR5) |
3200 Mbps (DDR4) |
2666 Mbps (DDR4) |
Maximum Ranks Supported |
2 |
2 |
4 |
4 |
Debug Features
EMIF Debug toolkit features include the below basic and advanced debug capabilities:
- Viewing calibration margin, status, pin delay and VREF settings
- Re-running calibration, traffic generator, and driver margining
- Updating delay settings, and termination settings
- Configurable Traffic Generator to send test traffic patterns
Related Links
Documentation
- Agilex™ 5 FPGA EMIF user guide ›
- Agilex™ 5 FPGA EMIF design example user guide ›
- Agilex™ 7 FPGA M-Series EMIF IP user guide ›
- Agilex™ 7 FPGA M-Series EMIF design example user guide ›
- Agilex™ 7 FPGA F-Series and I-Series EMIF IP user guide ›
- Agilex™ 7 FPGA F-Series and I-Series EMIF design example user guide ›
- Stratix® 10 EMIF user guide ›
- Stratix® 10 FPGA EMIF design example user guide ›
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