GMAC Register Group Register Descriptions

GMAC Register Group

Offset: 0x0

MAC_Configuration
The MAC Configuration register establishes receive and transmit operating modes.
MAC_Frame_Filter
The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.
GMII_Address
The GMII Address register controls the management cycles to the external PHY through the management interface.
GMII_Data
The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4.
Flow_Control
The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control block. A Write to a register with the gb bit (busy bit) of the GMII_Address register set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The gb bit of the GMII_Address register remains set until the control frame is transferred onto the cable. The Host must make sure that the gb bit is cleared before writing to the register.
VLAN_Tag
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with 16'h8100, and the following two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive frame status. The legal length of the frame is increased from 1,518 bytes to 1,522 bytes. Because the VLAN Tag register is double-synchronized to the (G)MII clock domain, then consecutive writes to these register should be performed only after at least four clock cycles in the destination clock domain.
Version
The Version registers identifies the version of the EMAC. This register contains two bytes: one specified by Synopsys to identify the core release number, and the other specified by Altera.
Debug
The Debug register gives the status of all main blocks of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths.
LPI_Control_Status
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
LPI_Timers_Control
The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.
Interrupt_Status
The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding optional feature is enabled.
Interrupt_Mask
The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o.
MAC_Address0_High
The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. Because the MAC address registers are double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
MAC_Address0_Low
The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address of the station.
MAC_Address1_High
The MAC Address1 High register holds the upper 16 bits of the 2nd 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address1 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address1_Low
The MAC Address1 Low register holds the lower 32 bits of the 2nd 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address2_High
The MAC Address2 High register holds the upper 16 bits of the 3rd 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address2 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address2_Low
The MAC Address2 Low register holds the lower 32 bits of the 3rd 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address3_High
The MAC Address3 High register holds the upper 16 bits of the 4th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address3 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address3_Low
The MAC Address3 Low register holds the lower 32 bits of the 4th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address4_High
The MAC Address4 High register holds the upper 16 bits of the 5th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address4 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address4_Low
The MAC Address4 Low register holds the lower 32 bits of the 5th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address5_High
The MAC Address5 High register holds the upper 16 bits of the 6th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address5 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address5_Low
The MAC Address5 Low register holds the lower 32 bits of the 6th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address6_High
The MAC Address6 High register holds the upper 16 bits of the 7th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address6 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address6_Low
The MAC Address6 Low register holds the lower 32 bits of the 7th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address7_High
The MAC Address7 High register holds the upper 16 bits of the 8th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address7 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address7_Low
The MAC Address7 Low register holds the lower 32 bits of the 8th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address8_High
The MAC Address8 High register holds the upper 16 bits of the 9th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address8 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address8_Low
The MAC Address8 Low register holds the lower 32 bits of the 9th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address9_High
The MAC Address9 High register holds the upper 16 bits of the 10th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address9 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address9_Low
The MAC Address9 Low register holds the lower 32 bits of the 10th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address10_High
The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address10 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address10_Low
The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address11_High
The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address11 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address11_Low
The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address12_High
The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address12 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address12_Low
The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address13_High
The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address13 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address13_Low
The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address14_High
The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address14 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address14_Low
The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address15_High
The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address15_Low
The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
SGMII_RGMII_SMII_Control_Status
The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY.
MMC_Control
The MMC Control register establishes the operating mode of the management counters. Note: The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
MMC_Receive_Interrupt
The MMC Receive Interrupt register maintains the interrupts that are generated when the following happens: * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter). * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When the Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
MMC_Transmit_Interrupt
The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
MMC_Receive_Interrupt_Mask
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.
MMC_Transmit_Interrupt_Mask
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.
txoctetcount_gb
Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames
txframecount_gb
Number of good and bad frames transmitted, exclusive of retried frames
txbroadcastframes_g
Number of good broadcast frames transmitted
txmulticastframes_g
Number of good multicast frames transmitted
tx64octets_gb
Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames
tx65to127octets_gb
Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames
tx128to255octets_gb
Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames
tx256to511octets_gb
Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames
tx512to1023octets_gb
Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames
tx1024tomaxoctets_gb
Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames
txunicastframes_gb
Number of good and bad unicast frames transmitted
txmulticastframes_gb
Number of good and bad multicast frames transmitted
txbroadcastframes_gb
Number of good and bad broadcast frames transmitted
txunderflowerror
Number of frames aborted due to frame underflow error
txsinglecol_g
Number of successfully transmitted frames after a single collision in Half-duplex mode
txmulticol_g
Number of successfully transmitted frames after more than a single collision in Half-duplex mode
txdeferred
Number of successfully transmitted frames after a deferral in Halfduplex mode
txlatecol
Number of frames aborted due to late collision error
txexesscol
Number of frames aborted due to excessive (16) collision errors
txcarriererr
Number of frames aborted due to carrier sense error (no carrier or loss of carrier)
txoctetcnt
Number of bytes transmitted, exclusive of preamble, in good frames only
txframecount_g
Number of good frames transmitted
txexcessdef
Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times)
txpauseframes
Number of good PAUSE frames transmitted
txvlanframes_g
Number of good VLAN frames transmitted, exclusive of retried frames
txoversize_g
Number of good and bad frames received
rxframecount_gb
Number of good and bad frames received
rxoctetcount_gb
Number of bytes received, exclusive of preamble, in good and bad frames
rxoctetcount_g
Number of bytes received, exclusive of preamble, only in good frames
rxbroadcastframes_g
Number of good broadcast frames received
rxmulticastframes_g
Number of good multicast frames received
rxcrcerror
Number of frames received with CRC error
rxalignmenterror
Number of frames received with alignment (dribble) error. Valid only in 10/100 mode
rxrunterror
Number of frames received with runt (<64 bytes and CRC error) error
rxjabbererror
Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames
rxundersize_g
Number of frames received with length less than 64 bytes, without any errors
rxoversize_g
Number of frames received with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames), without errors
rx64octets_gb
Number of good and bad frames received with length 64 bytes, exclusive of preamble
rx65to127octets_gb
Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble
rx128to255octets_gb
Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble
rx256to511octets_gb
Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble
rx512to1023octets_gb
Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble
rx1024tomaxoctets_gb
Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames
rxunicastframes_g
Number of good unicast frames received
rxlengtherror
Number of frames received with length error (length type field not equal to frame size), for all frames with valid length field
rxoutofrangetype
Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536)
rxpauseframes
Number of good and valid PAUSE frames received
rxfifooverflow
Number of missed received frames due to FIFO overflow
rxvlanframes_gb
Number of good and bad VLAN frames received
rxwatchdogerror
Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2,048 bytes)
rxrcverror
Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. While "Receive Error" is applicable to all PHY interfaces, "Frame Extension Error" can occur only for PHY interfaces that support 1G half-duplex mode.
rxctrlframes_g
Number of received good control frames.
MMC_IPC_Receive_Interrupt_Mask
This register maintains the mask for the interrupt generated from the receive IPC statistic counters.
MMC_IPC_Receive_Interrupt
This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When the MMC IPC counter that caused the interrupt is read, its corresponding interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0]) must be read to clear the interrupt bit.
rxipv4_gd_frms
Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
rxipv4_hdrerr_frms
Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors
rxipv4_nopay_frms
Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine
rxipv4_frag_frms
Number of good IPv4 datagrams with fragmentation
rxipv4_udsbl_frms
Number of good IPv4 datagrams received that had a UDP payload with checksum disabled
rxipv6_gd_frms
Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
rxipv6_hdrerr_frms
Number of IPv6 datagrams received with header errors (length or version mismatch)
rxipv6_nopay_frms
Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers
rxudp_gd_frms
Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented
rxudp_err_frms
Number of good IP datagrams whose UDP payload has a checksum error
rxtcp_gd_frms
Number of good IP datagrams with a good TCP payload
rxtcp_err_frms
Number of good IP datagrams whose TCP payload has a checksum error
rxicmp_gd_frms
Number of good IP datagrams with a good ICMP payload
rxicmp_err_frms
Number of good IP datagrams whose ICMP payload has a checksum error
rxipv4_gd_octets
Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data
rxipv4_hdrerr_octets
Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter
rxipv4_nopay_octets
Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter
rxipv4_frag_octets
Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter
rxipv4_udsbl_octets
Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes
rxipv6_gd_octets
Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data
rxipv6_hdrerr_octets
Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 headers Length field is used to update this counter
rxipv6_nopay_octets
Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter
rxudp_gd_octets
Number of bytes received in a good UDP segment. This counter does not count IP header bytes
rxudp_err_octets
Number of bytes received in a UDP segment that had checksum errors
rxtcp_gd_octets
Number of bytes received in a good TCP segment
rxtcperroctets
Number of bytes received in a TCP segment with checksum errors
rxicmp_gd_octets
Number of bytes received in a good ICMP segment
rxicmp_err_octets
Number of bytes received in an ICMP segment with checksum errors
L3_L4_Control0
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Layer4_Address0
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
Layer3_Addr0_Reg0
For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg0
For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr2_Reg0
For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg0
For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.
L3_L4_Control1
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Layer4_Address1
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
Layer3_Addr0_Reg1
For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg1
For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field
Layer3_Addr2_Reg1
For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg1
For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.
L3_L4_Control2
This register controls the operations of the filter 2 of Layer 3 and Layer 4.
Layer4_Address2
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
Layer3_Addr0_Reg2
For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg2
For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr2_Reg2
For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg2
For IPv4 frames, the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.
L3_L4_Control3
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Layer4_Address3
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
Layer3_Addr0_Reg3
For IPv4 frames, the Layer 3 Address 0 Register 3 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg3
For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP Destination Address field. For IPv6 frames, it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr2_Reg3
For IPv4 frames, the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames, it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg3
For IPv4 frames, the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames, it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field.
Hash_Table_Reg0
This register contains the first 32 bits of the hash table. The 256-bit Hash table is used for group address filtering. For hash filtering, the content of the destination address in the incoming frame is passed through the CRC logic and the upper eight bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register. For example, a hash value of 8b'10111111 selects Bit 31 of the Hash Table Register 5. The hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the multicast hash values. Because the Hash Table register is double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. Note: Because of double-synchronization, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.
Hash_Table_Reg1
This register contains the second 32 bits of the hash table.
Hash_Table_Reg2
This register contains the third 32 bits of the hash table.
Hash_Table_Reg3
This register contains the fourth 32 bits of the hash table.
Hash_Table_Reg4
This register contains the fifth 32 bits of the hash table.
Hash_Table_Reg5
This register contains the sixth 32 bits of the hash table.
Hash_Table_Reg6
This register contains the seventh 32 bits of the hash table.
Hash_Table_Reg7
This register contains the eighth 32 bits of the hash table.
VLAN_Hash_Table_Reg
The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN Tag Register) in the incoming frame is passed through the CRC logic and the upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash table. The hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the VLAN tag or ID (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper four bits from the value obtained in Step 2. If the corresponding bit value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. Because the Hash Table register is double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. Notes: * Because of double-synchronization, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.
Timestamp_Control
This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.
Sub_Second_Increment
In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this register is added to the system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
System_Time_Seconds
The System Time -Seconds register, along with System-TimeNanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from clk_ptp_ref_i to l3_sp_clk).
System_Time_Nanoseconds
The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero.
System_Time_Seconds_Update
The System Time - Seconds Update register, along with the System Time - Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both of these registers before setting the TSINIT or TSUPDT bits in the Timestamp Control register.
System_Time_Nanoseconds_Update
Update system time
Timestamp_Addend
This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in Register 448). This register content is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time is updated whenever the accumulator overflows.
Target_Time_Seconds
The Target Time Seconds register, along with Target Time Nanoseconds register, is used to schedule an interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the system time exceeds the value programmed in these registers.
Target_Time_Nanoseconds
Target time
System_Time_Higher_Word_Seconds
System time higher word
Timestamp_Status
Timestamp status. All bits except Bits[27:25] get cleared when the host reads this register.
PPS_Control
Controls timestamp Pulse-Per-Second output
Auxiliary_Timestamp_Nanoseconds
This register, along with Register 461 (Auxiliary Timestamp Seconds Register), gives the 64-bit timestamp stored as auxiliary snapshot. The two registers together form the read port of a 64-bit wide FIFO with a depth of 16. Multiple snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status register indicate the fill-level of this FIFO. The top of the FIFO is removed only when the last byte of Register 461 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read. In big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461 (Auxiliary Timestamp - Seconds Register).
Auxiliary_Timestamp_Seconds
Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
PPS0_Interval
The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).
PPS0_Width
The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0]).
MAC_Address16_High
The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address16 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address16_Low
The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address17_High
The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address17 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address17_Low
The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address18_High
The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address18 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address18_Low
The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address19_High
The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address19 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address19_Low
The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address20_High
The MAC Address20 High register holds the upper 16 bits of the 21th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address20 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address20_Low
The MAC Address20 Low register holds the lower 32 bits of the 21th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address21_High
The MAC Address21 High register holds the upper 16 bits of the 22th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address21 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address21_Low
The MAC Address21 Low register holds the lower 32 bits of the 22th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address22_High
The MAC Address22 High register holds the upper 16 bits of the 23th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address22 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address22_Low
The MAC Address22 Low register holds the lower 32 bits of the 23th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address23_High
The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address23 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address23_Low
The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address24_High
The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address24 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address24_Low
The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address25_High
The MAC Address25 High register holds the upper 16 bits of the 26th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address25 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address25_Low
The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address26_High
The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address26 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address26_Low
The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address27_High
The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address27 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address27_Low
The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address28_High
The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address28 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address28_Low
The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address29_High
The MAC Address29 High register holds the upper 16 bits of the 30th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address29 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address29_Low
The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address30_High
The MAC Address30 High register holds the upper 16 bits of the 31th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address30 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address30_Low
The MAC Address30 Low register holds the lower 32 bits of the 31th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address31_High
The MAC Address31 High register holds the upper 16 bits of the 32th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address31 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address31_Low
The MAC Address31 Low register holds the lower 32 bits of the 32th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address32_High
The MAC Address32 High register holds the upper 16 bits of the 33th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address32 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address32_Low
The MAC Address32 Low register holds the lower 32 bits of the 33th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address33_High
The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address33 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address33_Low
The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address34_High
The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address34 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address34_Low
The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address35_High
The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address35 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address35_Low
The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address36_High
The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address36 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address36_Low
The MAC Address36 Low register holds the lower 32 bits of the 37th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address37_High
The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address37 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address37_Low
The MAC Address37 Low register holds the lower 32 bits of the 38th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address38_High
The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address38 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address38_Low
The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address39_High
The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address39 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address39_Low
The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address40_High
The MAC Address40 High register holds the upper 16 bits of the 41th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address40 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address40_Low
The MAC Address40 Low register holds the lower 32 bits of the 41th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address41_High
The MAC Address41 High register holds the upper 16 bits of the 42th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address41 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address41_Low
The MAC Address41 Low register holds the lower 32 bits of the 42th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address42_High
The MAC Address42 High register holds the upper 16 bits of the 43th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address42 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address42_Low
The MAC Address42 Low register holds the lower 32 bits of the 43th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address43_High
The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address43 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address43_Low
The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address44_High
The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address44 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address44_Low
The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address45_High
The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address45 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address45_Low
The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address46_High
The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address46 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address46_Low
The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address47_High
The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address47 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address47_Low
The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address48_High
The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address48 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address48_Low
The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address49_High
The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address49 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address49_Low
The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address50_High
The MAC Address50 High register holds the upper 16 bits of the 51th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address50 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address50_Low
The MAC Address50 Low register holds the lower 32 bits of the 51th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address51_High
The MAC Address51 High register holds the upper 16 bits of the 52th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address51 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address51_Low
The MAC Address51 Low register holds the lower 32 bits of the 52th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address52_High
The MAC Address52 High register holds the upper 16 bits of the 53th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address52 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address52_Low
The MAC Address52 Low register holds the lower 32 bits of the 53th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address53_High
The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address53 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address53_Low
The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address54_High
The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address54 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address54_Low
The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address55_High
The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address55 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address55_Low
The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address56_High
The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address56 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address56_Low
The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address57_High
The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address57 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address57_Low
The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address58_High
The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address58 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address58_Low
The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address59_High
The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address59 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address59_Low
The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address60_High
The MAC Address60 High register holds the upper 16 bits of the 61th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address60 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address60_Low
The MAC Address60 Low register holds the lower 32 bits of the 61th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address61_High
The MAC Address61 High register holds the upper 16 bits of the 62th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address61 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address61_Low
The MAC Address61 Low register holds the lower 32 bits of the 62th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address62_High
The MAC Address62 High register holds the upper 16 bits of the 63th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address62 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address62_Low
The MAC Address62 Low register holds the lower 32 bits of the 63th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address63_High
The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address63 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address63_Low
The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address64_High
The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address64 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address64_Low
The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address65_High
The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address65 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address65_Low
The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address66_High
The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address66 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address66_Low
The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address67_High
The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address67 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address67_Low
The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address68_High
The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address68 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address68_Low
The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address69_High
The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address69 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address69_Low
The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address70_High
The MAC Address70 High register holds the upper 16 bits of the 71th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address70 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address70_Low
The MAC Address70 Low register holds the lower 32 bits of the 71th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address71_High
The MAC Address71 High register holds the upper 16 bits of the 72th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address71 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address71_Low
The MAC Address71 Low register holds the lower 32 bits of the 72th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address72_High
The MAC Address72 High register holds the upper 16 bits of the 73th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address72 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address72_Low
The MAC Address72 Low register holds the lower 32 bits of the 73th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address73_High
The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address73 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address73_Low
The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address74_High
The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address74 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address74_Low
The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address75_High
The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address75 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address75_Low
The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address76_High
The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address76 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address76_Low
The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address77_High
The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address77 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address77_Low
The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address78_High
The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address78 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address78_Low
The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address79_High
The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address79 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address79_Low
The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address80_High
The MAC Address80 High register holds the upper 16 bits of the 81th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address80 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address80_Low
The MAC Address80 Low register holds the lower 32 bits of the 81th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address81_High
The MAC Address81 High register holds the upper 16 bits of the 82th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address81 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address81_Low
The MAC Address81 Low register holds the lower 32 bits of the 82th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address82_High
The MAC Address82 High register holds the upper 16 bits of the 83th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address82 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address82_Low
The MAC Address82 Low register holds the lower 32 bits of the 83th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address83_High
The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address83 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address83_Low
The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address84_High
The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address84 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address84_Low
The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address85_High
The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address85 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address85_Low
The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address86_High
The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address86 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address86_Low
The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address87_High
The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address87 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address87_Low
The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address88_High
The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address88 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address88_Low
The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address89_High
The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address89 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address89_Low
The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address90_High
The MAC Address90 High register holds the upper 16 bits of the 91th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address90 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address90_Low
The MAC Address90 Low register holds the lower 32 bits of the 91th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address91_High
The MAC Address91 High register holds the upper 16 bits of the 92th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address91 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address91_Low
The MAC Address91 Low register holds the lower 32 bits of the 92th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address92_High
The MAC Address92 High register holds the upper 16 bits of the 93th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address92 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address92_Low
The MAC Address92 Low register holds the lower 32 bits of the 93th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address93_High
The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address93 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address93_Low
The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address94_High
The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address94 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address94_Low
The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address95_High
The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address95 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address95_Low
The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address96_High
The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address96 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address96_Low
The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address97_High
The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address97 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address97_Low
The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address98_High
The MAC Address98 High register holds the upper 16 bits of the 99th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address98 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address98_Low
The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address99_High
The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address99 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address99_Low
The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address100_High
The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address100 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address100_Low
The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address101_High
The MAC Address101 High register holds the upper 16 bits of the 102th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address101 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address101_Low
The MAC Address101 Low register holds the lower 32 bits of the 102th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address102_High
The MAC Address102 High register holds the upper 16 bits of the 103th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address102 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address102_Low
The MAC Address102 Low register holds the lower 32 bits of the 103th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address103_High
The MAC Address103 High register holds the upper 16 bits of the 104th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address103 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address103_Low
The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address104_High
The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address104 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address104_Low
The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address105_High
The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address105 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address105_Low
The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address106_High
The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address106 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address106_Low
The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address107_High
The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address107 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address107_Low
The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address108_High
The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address108 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address108_Low
The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address109_High
The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address109 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address109_Low
The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address110_High
The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address110 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address110_Low
The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address111_High
The MAC Address111 High register holds the upper 16 bits of the 112th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address111 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address111_Low
The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address112_High
The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address112 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address112_Low
The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address113_High
The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address113 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address113_Low
The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address114_High
The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address114 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address114_Low
The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address115_High
The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address115 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address115_Low
The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address116_High
The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address116 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address116_Low
The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address117_High
The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address117 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address117_Low
The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address118_High
The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address118 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address118_Low
The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address119_High
The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address119 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address119_Low
The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address120_High
The MAC Address120 High register holds the upper 16 bits of the 121th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address120 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address120_Low
The MAC Address120 Low register holds the lower 32 bits of the 121th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address121_High
The MAC Address121 High register holds the upper 16 bits of the 122th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address121 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address121_Low
The MAC Address121 Low register holds the lower 32 bits of the 122th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address122_High
The MAC Address122 High register holds the upper 16 bits of the 123th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address122 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address122_Low
The MAC Address122 Low register holds the lower 32 bits of the 123th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address123_High
The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address123 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address123_Low
The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address124_High
The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address124 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address124_Low
The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address125_High
The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address125 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address125_Low
The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address126_High
The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address126 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address126_Low
The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address127_High
The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC address of the station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address127 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High) have the same format.
MAC_Address127_Low
The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC address of the station. Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.

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