Timestamp_Control

This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700700
emac1 0xFF702000 0xFF702700

Offset: 0x700

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

atsen0

RW 0x0

atsfc

RW 0x0

Reserved

tsenmacaddr

RW 0x0

snaptypsel

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

tsmstrena

RW 0x0

tsevntena

RW 0x0

tsipv4ena

RW 0x1

tsipv6ena

RW 0x0

tsipena

RW 0x0

tsver2ena

RW 0x0

tsctrlssr

RW 0x0

tsenall

RW 0x0

Reserved

tsaddreg

RW 0x0

tstrig

RW 0x0

tsupdt

RW 0x0

tsinit

RW 0x0

tscfupdt

RW 0x0

tsena

RW 0x0

Timestamp_Control Fields

Bit Name Description Access Reset
25 atsen0

This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored.

Value Description
0x0 Auxiliary snapshot of event on ptp_aux_trig_i[0] input is disabled.
0x1 Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled.
RW 0x0
24 atsfc

When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO.

Value Description
0x0 Don't reset Auxiliary Snapshot FIFO pointers
0x1 Reset Auxiliary Snapshot FIFO pointers
RW 0x0
18 tsenmacaddr

When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet.

Value Description
0x0 DA MAC address doesn't filter PTP frames
0x1 DA MAC address filters PTP frames
RW 0x0
17:16 snaptypsel

These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken.

RW 0x0
15 tsmstrena

When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node.

Value Description
0x0 Timestamp snapshot taken for messages relevant to slave node
0x1 Timestamp snapshot taken for messages relevant to master node
RW 0x0
14 tsevntena

When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling.

Value Description
0x0 Timestamp snapshot disabled for event messages
0x1 Timestamp snapshot only for event messages
RW 0x0
13 tsipv4ena

When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default.

Value Description
0x0 Don't process PTP packets in UDP over IPv4
0x1 Process PTP packets in UDP over IPv4
RW 0x1
12 tsipv6ena

When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets.

Value Description
0x0 Don't process PTP packets in UDP over IPv6
0x1 Process PTP packets in UDP over IPv6
RW 0x0
11 tsipena

When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets.

Value Description
0x0 Don't process PTP packets in Ethernet frames
0x1 Process PTP packets in Ethernet frames
RW 0x0
10 tsver2ena

When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format.

Value Description
0x0 PTP packets processed with 1588 version 1 format
0x1 PTP packets processed with 1588 version 2 format
RW 0x0
9 tsctrlssr

When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit.

Value Description
0x0 Timestamp Low register rolls over at 0x7FFF_FFFF
0x1 Timestamp Low register rolls over at 1ns
RW 0x0
8 tsenall

When set, the timestamp snapshot is enabled for all frames received by the MAC.

Value Description
0x0 Timestamp snapshot disabled
0x1 Timestamp snapshot enabled
RW 0x0
5 tsaddreg

When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it.

Value Description
0x0 Timestamp Addend register is not updated
0x1 Timestamp Addend register is updated
RW 0x0
4 tstrig

When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt.

Value Description
0x0 Timestamp not generated
0x1 Timestamp generated
RW 0x0
3 tsupdt

When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The Timestamp Higher Word register is not updated.

Value Description
0x0 Timestamp not updated (added or subtracted) with values in Register 452 and Register 453
0x1 Timestamp updated (added or subtracted) with values in Register 452 and Register 453
RW 0x0
2 tsinit

When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The Timestamp Higher Word register can only be initialized.

Value Description
0x0 Timestamp not initialized (overwritten) by values in Register 452 and Register 453
0x1 Timestamp initialized (overwritten) by values in Register 452 and Register 453
RW 0x0
1 tscfupdt

When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method.

Value Description
0x0 Timestamp Coarse
0x1 Timestamp Fine
RW 0x0
0 tsena

When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set.

Value Description
0x0 Timestamp not added
0x1 Timestamp added for transmit and receive
RW 0x0