MMC_IPC_Receive_Interrupt_Mask

This register maintains the mask for the interrupt generated from the receive IPC statistic counters.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700200
emac1 0xFF702000 0xFF702200

Offset: 0x200

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

rxicmperoim

RW 0x0

rxicmpgoim

RW 0x0

rxtcperoim

RW 0x0

rxtcpgoim

RW 0x0

rxudperoim

RW 0x0

rxudpgoim

RW 0x0

rxipv6nopayoim

RW 0x0

rxipv6heroim

RW 0x0

rxipv6goim

RW 0x0

rxipv4udsbloim

RW 0x0

rxipv4fragoim

RW 0x0

rxipv4nopayoim

RW 0x0

rxipv4heroim

RW 0x0

rxipv4goim

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxicmperfim

RW 0x0

rxicmpgfim

RW 0x0

rxtcperfim

RW 0x0

rxtcpgfim

RW 0x0

rxudperfim

RW 0x0

rxudpgfim

RW 0x0

rxipv6nopayfim

RW 0x0

rxipv6herfim

RW 0x0

rxipv6gfim

RW 0x0

rxipv4udsblfim

RW 0x0

rxipv4fragfim

RW 0x0

rxipv4nopayfim

RW 0x0

rxipv4herfim

RW 0x0

rxipv4gfim

RW 0x0

MMC_IPC_Receive_Interrupt_Mask Fields

Bit Name Description Access Reset
29 rxicmperoim

Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
28 rxicmpgoim

Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
27 rxtcperoim

Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
26 rxtcpgoim

Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
25 rxudperoim

Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
24 rxudpgoim

Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
23 rxipv6nopayoim

Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
22 rxipv6heroim

Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
21 rxipv6goim

Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
20 rxipv4udsbloim

Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
19 rxipv4fragoim

Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
18 rxipv4nopayoim

Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
17 rxipv4heroim

Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
16 rxipv4goim

Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
13 rxicmperfim

Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
12 rxicmpgfim

Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
11 rxtcperfim

Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
10 rxtcpgfim

Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
9 rxudperfim

Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
8 rxudpgfim

Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
7 rxipv6nopayfim

Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
6 rxipv6herfim

Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
5 rxipv6gfim

Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
4 rxipv4udsblfim

Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
3 rxipv4fragfim

Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
2 rxipv4nopayfim

Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
1 rxipv4herfim

Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0
0 rxipv4gfim

Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value.

Value Description
0x0 counter < half max
0x1 counter >= half max or max
RW 0x0