MMC_Transmit_Interrupt_Mask
| Module Instance | Base Address | Register Address |
|---|---|---|
| emac0 | 0xFF700000 | 0xFF700110 |
| emac1 | 0xFF702000 | 0xFF702110 |
Offset: 0x110
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
txosizegfim RW 0x0 |
txvlangfim RW 0x0 |
txpausfim RW 0x0 |
txexdeffim RW 0x0 |
txgfrmim RW 0x0 |
txgoctim RW 0x0 |
txcarerfim RW 0x0 |
txexcolfim RW 0x0 |
txlatcolfim RW 0x0 |
txdeffim RW 0x0 |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
txmcolgfim RW 0x0 |
txscolgfim RW 0x0 |
txuflowerfim RW 0x0 |
txbcgbfim RW 0x0 |
txmcgbfim RW 0x0 |
txucgbfim RW 0x0 |
tx1024tmaxoctgbfim RW 0x0 |
tx512t1023octgbfim RW 0x0 |
tx256t511octgbfim RW 0x0 |
tx128t255octgbfim RW 0x0 |
tx65t127octgbfim RW 0x0 |
tx64octgbfim RW 0x0 |
txmcgfim RW 0x0 |
txbcgfim RW 0x0 |
txgbfrmim RW 0x0 |
txgboctim RW 0x0 |
MMC_Transmit_Interrupt_Mask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 25 | txosizegfim | Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 24 | txvlangfim | Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 23 | txpausfim | Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 22 | txexdeffim | Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 21 | txgfrmim | Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 20 | txgoctim | Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 19 | txcarerfim | Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 18 | txexcolfim | Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 17 | txlatcolfim | Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 16 | txdeffim | Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 15 | txmcolgfim | Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 14 | txscolgfim | Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 13 | txuflowerfim | Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 12 | txbcgbfim | Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 11 | txmcgbfim | Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 10 | txucgbfim | Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 9 | tx1024tmaxoctgbfim | Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 8 | tx512t1023octgbfim | Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 7 | tx256t511octgbfim | Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 6 | tx128t255octgbfim | Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 5 | tx65t127octgbfim | Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 4 | tx64octgbfim | Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 3 | txmcgfim | Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 2 | txbcgfim | Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 1 | txgbfrmim | Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 0 | txgboctim | Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 |