Debug

The Debug register gives the status of all main blocks of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data-paths.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700024
emac1 0xFF702000 0xFF702024

Offset: 0x24

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

txstsfsts

RO 0x0

txfsts

RO 0x0

Reserved

twcsts

RO 0x0

trcsts

RO 0x0

txpaused

RO 0x0

tfcsts

RO 0x0

tpests

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxfsts

RO 0x0

Reserved

rrcsts

RO 0x0

rwcsts

RO 0x0

Reserved

rfcfcsts

RO 0x0

rpests

RO 0x0

Debug Fields

Bit Name Description Access Reset
25 txstsfsts

When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission.

Value Description
0x0 MTL TxStatus FIFO Not Full Status
0x1 MTL TxStatus FIFO Full Status
RO 0x0
24 txfsts

When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission.

Value Description
0x0 MTL Tx FIFO Empty
0x1 MTL Tx FIFO Not Empty
RO 0x0
22 twcsts

When high, this bit indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx FIFO.

Value Description
0x0 Tx FIFO Write Ctrl Inactive
0x1 Tx FIFO Write Ctrl Active
RO 0x0
21:20 trcsts

This field indicates the state of the Tx FIFO Read Controller

Value Description
0x0 Idle State
0x1 Read State (transferring data to the MAC transmitter)
0x2 Waiting for TxStatus from the MAC transmitter
0x3 Writing the received TxStatus or flushing the Tx FIFO
RO 0x0
19 txpaused

When high, this bit indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission.

Value Description
0x0 MAC Transmitter Pause Disabled
0x1 MAC Transmitter Pause Condition
RO 0x0
18:17 tfcsts

This field indicates the state of the MAC Transmit Frame Controller block

Value Description
0x0 Idle State
0x1 Waiting Prev. State or IFG
0x2 Generating Tx Pause
0x3 Tx Input Frame
RO 0x0
16 tpests

When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state.

Value Description
0x0 Idle State
0x1 Actively Transmitting Data
RO 0x0
9:8 rxfsts

This field gives the status of the fill-level of the Rx FIFO.

Value Description
0x0 Rx FIFO Empty
0x1 Rx FIFO fill-level below flow-control deactivate thres.
0x2 Rx FIFO fill-level above flow-control activate thres.
0x3 Rx FIFO Full
RO 0x0
6:5 rrcsts

This field gives the state of the Rx FIFO read Controller

Value Description
0x0 IDLE State
0x1 Reading Frame Data
0x2 Reading Frame Status (or timestamp)
0x3 Flushing Frame Data and Status
RO 0x0
4 rwcsts

When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.

Value Description
0x0 MTL Rx Fifo Controller Non-Active Status
0x1 MTL Rx Fifo Controller Active Status
RO 0x0
2:1 rfcfcsts

When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module.

Value Description
0x0 Disable Active State FIFO Read Write
0x1 Enable Active State FIFO Read Write
RO 0x0
0 rpests

When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state.

Value Description
0x0 Idle State
0x1 Protocol Engine Active
RO 0x0