LPI_Timers_Control

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF700034`
`emac1`	`0xFF702000`	`0xFF702034`

Offset: 0x34

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`						`lst` `RW 0x3E8`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`twt` `RW 0x0`

LPI_Timers_Control Fields

Bit	Name	Description	Access	Reset
25:16	`lst`	This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard.	`RW`	`0x3E8`
15:0	`twt`	This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.	`RW`	`0x0`