Interrupt_Mask

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF70003C
emac1 0xFF702000 0xFF70203C

Offset: 0x3C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

lpiim

RW 0x0

tsim

RW 0x0

Reserved

pcsancim

RO 0x0

pcslchgim

RO 0x0

rgsmiiim

RW 0x0

Interrupt_Mask Fields

Bit Name Description Access Reset
10 lpiim

When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register).

Value Description
0x0 LPI Interrupt Mask Disabled
0x1 LPI Interrupt Mask Enabled
RW 0x0
9 tsim

When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register).

Value Description
0x0 Timestamp Interrupt Mask Disabled
0x1 Timestamp Interrupt Mask Enabled
RW 0x0
2 pcsancim

When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register).

RO 0x0
1 pcslchgim

When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register).

 RO 0x0
0 rgsmiiim

When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register).

Value Description
0x0 RGMII or SMII Interrupt Mask Disable
0x1 RGMII or SMII Interrupt Mask Enable
RW 0x0