rstmgr Address Map

Registers in the Reset Manager module


Module Instance	Base Address	End Address
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`	`0x10D11000`	`0x10D110FF`


Register	Offset	Width	Access	Reset Value	Description
`stat`	`0x0`	`32`	`RW`	`0x00000004`	Reset Status Register
`miscstat`	`0x8`	`32`	`RW`	`0x00000000`	Timeout Status Register
`hdsken`	`0x10`	`32`	`RW`	`0xFFFFFFFB`	Handshake Enable
`hdskreq`	`0x14`	`32`	`RW`	`0x00000000`	Handshake Request Register
`hdskack`	`0x18`	`32`	`RW`	`0x00000000`	Handshake Acknowledge Register
`hdskstall`	`0x1C`	`32`	`RW`	`0x00000000`	ETR Stall Status Register
`per0modrst`	`0x24`	`32`	`RW`	`0xFFFFFFFF`	Peripheral 0 Module Reset Register
`per1modrst`	`0x28`	`32`	`RW`	`0xFFFFFFFF`	Peripheral Module Reset Register
`brgmodrst`	`0x2C`	`32`	`RW`	`0xFFFFFFFF`	Bridge Reset Register
`dbgmodrst`	`0x3C`	`32`	`RW`	`0x00000000`	Debug Module Reset Register
`brgwarmmask`	`0x4C`	`32`	`RW`	`0x0000004F`	Bridge Warm Mask Register
`tststa`	`0x5C`	`32`	`RO`	`0x00000000`	Test Status
`hdsktimeout`	`0x64`	`32`	`RW`	`0x00002800`	Hand Shake Time Out Value
`dbghdsktimeout`	`0x6C`	`32`	`RW`	`0x00100000`	L3NOC Debug CS_DAP Handshake Time Out Value
`dbgrstcmplt`	`0x70`	`32`	`RW`	`0x00000000`	Reset Manager sets to 1 when a SW requested debug reset sequence is completed. Cleared by Reset Manager after SW clears dbgmodrst[dbg_rst]
`hpsrstcmplt`	`0x80`	`32`	`RW`	`0x00000000`
`cpuinreset`	`0x90`	`32`	`RO`	`0x00000000`	cpuinreset
`cpurstrelease`	`0x94`	`32`	`RW`	`0x00000000`	On Chip RAM load done
`cpu0_reset_base_low`	`0x98`	`32`	`RW`	`0x00000000`	cpu0_reset_base_low
`cpu0_reset_base_high`	`0x9C`	`32`	`RW`	`0x00000000`	Drives RVBARAAR0[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu1_reset_base_low`	`0xA0`	`32`	`RW`	`0x00000000`	Drives RVBARAAR1[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu1_reset_base_high`	`0xA4`	`32`	`RW`	`0x00000000`	Drives RVBARAAR1[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu2_reset_base_low`	`0xA8`	`32`	`RW`	`0x00000000`	Drives RVBARAAR2[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu2_reset_base_high`	`0xAC`	`32`	`RW`	`0x00000000`	Drives RVBARAAR2[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu3_reset_base_low`	`0xB0`	`32`	`RW`	`0x00000000`	Drives RVBARAAR3[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address
`cpu3_reset_base_high`	`0xB4`	`32`	`RW`	`0x00000000`	Drives RVBARAAR3[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address