cpuinreset

         The COLDMODRST register is used by software to trigger module resets. Writing 1 to any of these fields will cause the L2 or CPU POR reset signal to be asserted if that module is in WFI mode. The Reset Manager hardware will bring the module back out of reset after the appropriate amount of time.
 
All fields are only reset by a cold reset.


Module Instance	Base Address	Register Address
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`	`0x10D11000`	`0x10D11090`

Size: 32

Offset: 0x90

Access: RO

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_4` `RO 0x0`												`cpu3_in_reset` `RO 0x0`	`cpu2_in_reset` `RO 0x0`	`cpu1_in_reset` `RO 0x0`	`cpu0_in_reset` `RO 0x0`

cpuinreset Fields


Bit	Name	Description	Access	Reset
31:4	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
3	`cpu3_in_reset`	CPU3 in reset	`RO`	`0x0`
2	`cpu2_in_reset`	CPU2 in reset	`RO`	`0x0`
1	`cpu1_in_reset`	CPU1 in reset	`RO`	`0x0`
0	`cpu0_in_reset`	CPU0 in reset	`RO`	`0x0`