cpurstrelease 

         Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair
Module Instance Base Address Register Address
i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000 0x10D11000 0x10D11094

Size: 32

Offset: 0x94

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

cpu3_release

RW 0x0

cpu2_release

RW 0x0

cpu1_release

RW 0x0

cpu0_release

RW 0x0

cpurstrelease Fields

Bit Name Description Access Reset
31:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 cpu3_release 
Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair
 RW 0x0
2 cpu2_release 
A read-only status register. A 0x1 in a bit location indicates the associated core is available and still in warm reset. Used to indicate which other cores could be brought out of reset by writing to a cpurstrelease[cpux_release] bit.
 RW 0x0
1 cpu1_release 
Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair
 RW 0x0
0 cpu0_release 
SDM sets this bit to indicate the Reset Manager that the on chip ram loading is done and it is safe to proceed with the MPU reset de-assertion sequence.
RW 0x0