hdskreq 

         This register includes fields for software to initiate the handshake with certain peripherals. Software must clear the request bit except for "debug_l3noc_req" once it sees the corresponding acknowledge bit has been set in the hdskack register. "debug_l3noc_req" is cleared by hardware once the corresponding dbg_rst or csdap_rst is/are asserted. Software should implement its own timeout.
Fields are reset by a cold reset. It is recommended that software should clear this bit on every warm reset.
Module Instance Base Address Register Address
i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000 0x10D11000 0x10D11014

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

debug_l3noc_req

RW 0x0

l3noc_dbg_req

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_7

RO 0x0

f2s_flush_req

RW 0x0

f2sdram_flush_req

RW 0x0

soc2fpga_flush_req

RW 0x0

lwsoc2fpga_flush_req

RW 0x0

Reserved_3

RO 0x0

etrstallreq

RW 0x0

fpgahsreq

RW 0x0

Reserved_1

RO 0x0

emif_flush_req

RW 0x0

hdskreq Fields

Bit Name Description Access Reset
31:18 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
17 debug_l3noc_req 
This field controls whether to fence and drain CoreSight traffic before resetting CoreSight logic. This handshake is performed when CS DAP or/and DBG is getting reset but the HPS is not getting reset. If set to 1, the Reset Manager makes a handshake request to the PSS NOC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
16 l3noc_dbg_req 
This field controls whether to fence and drain CoreSight traffic before resetting the HPS. This handshake is performed when the HPS is getting reset but CoreSight logic not getting reset. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
15:13 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
12 f2s_flush_req 
This field controls whether to fence and drain traffic on the MPFE F2S ACE-lite port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
11 f2sdram_flush_req 
This field controls whether to fence and drain traffic on the MPFE F2SDRAM AXI4 port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
10 soc2fpga_flush_req 
This field controls whether to fence and drain traffic on the SOC2FPGA port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed
 RW 0x0
9 lwsoc2fpga_flush_req 
This field controls whether to fence and drain traffic on the LWSOC2FPGA port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
8:4 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
3 etrstallreq 
This field controls whether to fence and drain traffic on the Embedder Trace Router (ETR) before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
2 fpgahsreq 
This field controls whether to alert SoftLogic of a pending HPS reset. If set to 1, the Reset Manager makes a handshake request to the Fabric before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 emif_flush_req 
This field controls whether to fence and drain traffic to MPFE EMIF (and future H-NoC) ports before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0, the handshake is not performed
 RW 0x0