miscstat 

         The "miscstat" register contains bits that indicate the timeout event. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset.
After a cold reset is complete, all bits are reset to their reset value. A warm reset does not clear any of the bits in the "miscstat" register. These bits must be cleared by software writing 1 to the "miscstat" register.
Module Instance Base Address Register Address
i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000 0x10D11000 0x10D11008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

debugl3noctimeout

RW 0x0

l3nocdbgtimeout

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_7

RO 0x0

f2stimeout

RW 0x0

f2sdramtimeout

RW 0x0

soc2fpgatimeout

RW 0x0

lwsoc2fpgatimeout

RW 0x0

Reserved_3

RO 0x0

etrstalltimeout

RW 0x0

fpgahstimeout

RW 0x0

Reserved_1

RO 0x0

emiftimeout

RW 0x0

miscstat Fields

Bit Name Description Access Reset
31:18 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
17 debugl3noctimeout 
A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced reset timed-out and the Reset Manager had to proceed with the reset anyway.
RW 0x0
16 l3nocdbgtimeout 
A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway. Reset Manager performs this handshake with NOC when NOC is getting reset but debug logic does not get reset.
 RW 0x0
15:13 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
12 f2stimeout 
A 1 indicates that Reset Manager's handshake request to F2S(coherent ACE-lite port in MPFE) timed out and the Reset Manager proceeded with the hardware sequenced reset.
 RW 0x0
11 f2sdramtimeout 
A 1 indicates that Reset Manager's handshake request to F2SDRAM (non-coherent AXI port in MPFE) timed out and the Reset Manager proceeded with the hardware sequenced reset.
 RW 0x0
10 soc2fpgatimeout 
A 1 indicates that Reset Manager's handshake request to SOC2FPGA  timed out and the Reset Manager proceeded with the hardware sequenced reset.
 RW 0x0
9 lwsoc2fpgatimeout 
A 1 indicates that Reset Manager's handshake request to LWSOC2FPGA  timed out and the Reset Manager proceeded with the hardware sequenced reset.
 RW 0x0
8:4 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
3 etrstalltimeout 
A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0
2 fpgahstimeout 
A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0
1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 emiftimeout 
A 1 indicates that Reset Manager's handshake request to the SDRAM Controller Subsystem timed out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0