cpu1_reset_base_low

         Drives RVBARAAR1[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address


Module Instance	Base Address	Register Address
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`	`0x10D11000`	`0x10D110A0`

Size: 32

Offset: 0xA0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`		`vector_base_low` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`vector_base_low` `RW 0x0`

cpu1_reset_base_low Fields


Bit	Name	Description	Access	Reset
31:30	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
29:0	`vector_base_low`	CPU1 Reset vector address [31:02]	`RW`	`0x0`