hpsrstcmplt


Module Instance	Base Address	Register Address
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`	`0x10D11000`	`0x10D11080`

Size: 32

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`hpsrstcmplt` `RW 0x0`

hpsrstcmplt Fields

Bit Name Description Access Reset

31:1

Bit	Name	Description	Access	Reset
31:1	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
0	`hpsrstcmplt`	A status register indicating that an HPS reset sequence is waiting for further input from the SDM such as downloading the FSBL and/or writing a cpux_release bit. A first write to a cpurstrelease[cpux_release] bit clears this register.	`RW`	`0x0`

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

hpsrstcmplt

A status register indicating that an HPS reset sequence is waiting for further input from the SDM such as downloading the FSBL and/or writing a cpux_release bit. A first write to a cpurstrelease[cpux_release] bit clears this register.

RW

0x0