brgmodrst

         The BRGMODRST register is used by software to control the bridge module resets. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal.  
Software writes a bit to 1 to assert the module reset signal and to 0 to de-assert the module reset signal.
All fields are reset by a cold reset. All fields are also reset by a warm reset if not masked by the corresponding BRGWARMMASK field.
The reset value of all fields is 1. This holds the corresponding module in reset until software is ready to release the module from reset by writing 0 to its field.


Module Instance	Base Address	Register Address
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`	`0x10D11000`	`0x10D1102C`

Size: 32

Offset: 0x2C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_5` `RO 0x1FFFFFF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_5` `RO 0x1FFFFFF`									`mpfe` `RW 0x1`	`Reserved_4` `RO 0x3`		`fpga2sdram` `RW 0x1`	`fpga2soc` `RW 0x1`	`lwsoc2fpga` `RW 0x1`	`soc2fpga` `RW 0x1`

brgmodrst Fields


Bit	Name	Description	Access	Reset
31:7	`Reserved_5`	Reserved bitfield added by Magillem	`RO`	`0x1FFFFFF`
6	`mpfe`	Resets logic in the MPFE.	`RW`	`0x1`
5:4	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x3`
3	`fpga2sdram`	Resets fpga2sdram bridge	`RW`	`0x1`
2	`fpga2soc`	Resets FPGA2SOC Bridge.	`RW`	`0x1`
1	`lwsoc2fpga`	Resets LWHPS2FPGA Bridge.	`RW`	`0x1`
0	`soc2fpga`	Resets SOC2FPGA Bridge.	`RW`	`0x1`