rstmgr Summary

Registers in the Reset Manager module

Base Address: 0x10D11000


Register Address Offset	Bit Fields
`i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000`
`stat` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_10` `RO 0x0`						`csdaprst` `RW 0x0`	`debugrst` `RW 0x0`	`Reserved_8` `RO 0x0`			`l4wd4rst` `RW 0x0`	`l4wd3rst` `RW 0x0`	`l4wd2rst` `RW 0x0`	`l4wd1rst` `RW 0x0`	`l4wd0rst` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`													`sdmlastporrst` `RW 0x1`	`sdmwarmrst` `RW 0x0`	`sdmcoldrst` `RW 0x0`
`miscstat` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`														`debugl3noctimeout` `RW 0x0`	`l3nocdbgtimeout` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`			`f2stimeout` `RW 0x0`	`f2sdramtimeout` `RW 0x0`	`soc2fpgatimeout` `RW 0x0`	`lwsoc2fpgatimeout` `RW 0x0`	`Reserved_3` `RO 0x0`					`etrstalltimeout` `RW 0x0`	`fpgahstimeout` `RW 0x0`	`Reserved_1` `RO 0x0`	`emiftimeout` `RW 0x0`
`hdsken` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x3FFF`														`debug_l3noc` `RW 0x1`	`l3noc_dbg` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x7`			`f2soc_flush` `RW 0x1`	`f2sdram_flush` `RW 0x1`	`soc2fpga_flush` `RW 0x1`	`lwsoc2fpga_flush` `RW 0x1`	`Reserved_3` `RO 0x1F`					`etrstallen` `RW 0x1`	`fpgahsen` `RW 0x0`	`Reserved_1` `RO 0x1`	`emif_flush` `RW 0x1`
`hdskreq` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`														`debug_l3noc_req` `RW 0x0`	`l3noc_dbg_req` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`			`f2s_flush_req` `RW 0x0`	`f2sdram_flush_req` `RW 0x0`	`soc2fpga_flush_req` `RW 0x0`	`lwsoc2fpga_flush_req` `RW 0x0`	`Reserved_3` `RO 0x0`					`etrstallreq` `RW 0x0`	`fpgahsreq` `RW 0x0`	`Reserved_1` `RO 0x0`	`emif_flush_req` `RW 0x0`
`hdskack` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`														`debug_l3noc_ack` `RW 0x0`	`l3noc_dbg_ack` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`			`f2s_flush_ack` `RW 0x0`	`f2sdram_flush_ack` `RW 0x0`	`soc2fpga_flush_ack` `RW 0x0`	`lwsoc2fpga_flush_ack` `RW 0x0`	`Reserved_3` `RO 0x0`					`etrstallack` `RW 0x0`	`fpgahsack` `RW 0x0`	`Reserved_1` `RO 0x0`	`emif_flush_ack` `RW 0x0`
`hdskstall` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`etrstallwarmrst` `RW 0x0`
`per0modrst` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dmaif7` `RW 0x1`	`dmaif6` `RW 0x1`	`dmaif5` `RW 0x1`	`dmaif4` `RW 0x1`	`dmaif3` `RW 0x1`	`dmaif2` `RW 0x1`	`dmaif1` `RW 0x1`	`dmaif0` `RW 0x1`	`Reserved_22` `RO 0x1`	`emacptp` `RW 0x1`	`dmaecc` `RW 0x1`	`spis1` `RW 0x1`	`spis0` `RW 0x1`	`spim1` `RW 0x1`	`spim0` `RW 0x1`	`dma` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcecc` `RW 0x1`	`Reserved_14` `RO 0x1`	`nandecc` `RW 0x1`	`usb1ecc` `RW 0x1`	`usb0ecc` `RW 0x1`	`tsn2ecc` `RW 0x1`	`tsn1ecc` `RW 0x1`	`tsn0ecc` `RW 0x1`	`sdmmc` `RW 0x1`	`softphy` `RW 0x1`	`nand` `RW 0x1`	`usb1` `RW 0x1`	`usb0` `RW 0x1`	`tsn2` `RW 0x1`	`tsn1` `RW 0x1`	`tsn0` `RW 0x1`
`per1modrst` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_20` `RO 0x1F`					`watchdog4` `RW 0x1`	`gpio1` `RW 0x1`	`gpio0` `RW 0x1`	`Reserved_17` `RO 0x3F`						`uart1` `RW 0x1`	`uart0` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x1`	`i3c1` `RW 0x1`	`i3c0` `RW 0x1`	`i2c4` `RW 0x1`	`i2c3` `RW 0x1`	`i2c2` `RW 0x1`	`i2c1` `RW 0x1`	`i2c0` `RW 0x1`	`sptimer1` `RW 0x1`	`sptimer0` `RW 0x1`	`l4systimer1` `RW 0x1`	`l4systimer0` `RW 0x1`	`watchdog3` `RW 0x1`	`watchdog2` `RW 0x1`	`watchdog1` `RW 0x1`	`watchdog0` `RW 0x1`
`brgmodrst` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x1FFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x1FFFFFF`									`mpfe` `RW 0x1`	`Reserved_4` `RO 0x3`		`fpga2sdram` `RW 0x1`	`fpga2soc` `RW 0x1`	`lwsoc2fpga` `RW 0x1`	`soc2fpga` `RW 0x1`
`dbgmodrst` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`dbg_rst` `RW 0x0`
`brgwarmmask` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`									`mpfe` `RW 0x1`	`Reserved_4` `RO 0x0`		`fpga2sdram` `RW 0x1`	`fpga2soc` `RW 0x1`	`lwsoc2fpga` `RW 0x1`	`soc2fpga` `RW 0x1`
`tststa` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`											`rstst` `RO 0x0`
`hdsktimeout` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x2800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x2800`
`dbghdsktimeout` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x100000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x100000`
`dbgrstcmplt` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`swdbgrstcmplt` `RW 0x0`
`hpsrstcmplt` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`hpsrstcmplt` `RW 0x0`
`cpuinreset` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`cpu3_in_reset` `RO 0x0`	`cpu2_in_reset` `RO 0x0`	`cpu1_in_reset` `RO 0x0`	`cpu0_in_reset` `RO 0x0`
`cpurstrelease` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`cpu3_release` `RW 0x0`	`cpu2_release` `RW 0x0`	`cpu1_release` `RW 0x0`	`cpu0_release` `RW 0x0`
`cpu0_reset_base_low` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`vector_base_low` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`vector_base_low` `RW 0x0`
`cpu0_reset_base_high` `0x156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`vector_base_high` `RW 0x0`
`cpu1_reset_base_low` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`vector_base_low` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`vector_base_low` `RW 0x0`
`cpu1_reset_base_high` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`vector_base_high` `RW 0x0`
`cpu2_reset_base_low` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`vector_base_low` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`vector_base_low` `RW 0x0`
`cpu2_reset_base_high` `0x172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`vector_base_high` `RW 0x0`
`cpu3_reset_base_low` `0x176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`		`vector_base_low` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`vector_base_low` `RW 0x0`
`cpu3_reset_base_high` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`vector_base_high` `RW 0x0`