mainpllgrp Address Map

Contains registers with settings for the Main PLL.


Module Instance	Base Address	End Address
`i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D10024`	`0x10D1007B`


Register	Offset	Width	Access	Reset Value	Description
`en`	`0x0`	`32`	`RW`	`0x00000FFF`	Enable Register
`ens`	`0x4`	`32`	`RW`	`0x00000080`	Enable Set Register
`enr`	`0x8`	`32`	`RW`	`0x00000080`	Enable Reset Register
`bypass`	`0xC`	`32`	`RW`	`0x000000FF`	Bypass Register
`bypasss`	`0x10`	`32`	`RW`	`0x000000FF`	Bypass Set Register
`bypassr`	`0x14`	`32`	`RW`	`0x000000FF`	Bypass Reset Register
`nocclk`	`0x1C`	`32`	`RW`	`0x00000000`	Main PLL Control Register for NOC Clock Group.
`nocdiv`	`0x20`	`32`	`RW`	`0x20260198`	NoC Divide Register
`pllglob`	`0x24`	`32`	`RW`	`0x16000101`	This refects register settings for all the channels of the main PLL
`fdbck`	`0x28`	`32`	`RW`	`0x2A000000`	VCO freq register counters
`mem`	`0x2C`	`32`	`RW`	`0x00000000`	Registers dealing with PLL internal memory access.
`memstat`	`0x30`	`32`	`RW`	`0x00000000`	Main PLL memstatus register. contains memory read data
`vcocalib`	`0x34`	`32`	`RW`	`0x0001087C`	VCO calibration control registers.
`pllc0`	`0x38`	`32`	`RW`	`0x00000005`	Channel C0 frequency settings for the main PLL
`pllc1`	`0x3C`	`32`	`RW`	`0x00000004`	Channel C1 frequency settings for the main PLL
`pllc2`	`0x40`	`32`	`RW`	`0x00000007`	Channel C2 frequency settings for the main PLL
`pllc3`	`0x44`	`32`	`RW`	`0x00000008`	Channel C3 frequency settings for the main PLL
`pllm`	`0x48`	`32`	`RO`	`0x00000080`	Feedback Clock Divider Control (VCO Frequency Register Counters)
`fhop`	`0x4C`	`32`	`RO`	`0x00000000`	Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register.
`ssc`	`0x50`	`32`	`RO`	`0x00000000`	Spread Spectrum Clocking (SSC) Control and Status Registers.
`lostlock`	`0x54`	`32`	`RO`	`0x00000000`	To enable the keep alive clock to appear on the clock slice outputs when PLL lock is lost. By default, the clock slices are muted (bit = 0).