pllm

         Feedback Clock Divider Control (VCO Frequency Register Counters)


Module Instance	Base Address	Register Address
`i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D10024`	`0x10D1006C`

Size: 32

Offset: 0x48

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`						`mdiv` `RW 0x80`

pllm Fields

Bit Name Description Access Reset

31:10

Bit	Name	Description	Access	Reset
31:10	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
9:0	`mdiv`	Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state. It cannot be switched dynamically.	`RW`	`0x80`

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

9:0

mdiv

Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state. 
It cannot be switched dynamically.

RW

0x80