enr

         Write One to Clear corresponding fields in Enable Register.


Module Instance	Base Address	Register Address
`i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D10024`	`0x10D1002C`

Size: 32

Offset: 0x8

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_9` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_9` `RO 0x0`				`core3en` `RW 0x0`	`core2en` `RW 0x0`	`core1en` `RW 0x0`	`core0en` `RW 0x0`	`Reserved_5` `RO 0x1`	`s2fuser0clken` `RW 0x0`	`Reserved_4` `RO 0x0`	`csclken` `RW 0x0`	`l4spclken` `RW 0x0`	`l4mpclken` `RW 0x0`	`l4mainclken` `RW 0x0`	`Reserved_0` `RO 0x0`

enr Fields


Bit	Name	Description	Access	Reset
31:12	`Reserved_9`	Reserved bitfield added by Magillem	`RO`	`0x0`
11	`core3en`	core 3 clock enable	`RW`	`0x0`
10	`core2en`	core 2 clock enable	`RW`	`0x0`
9	`core1en`	core 1 clock enable	`RW`	`0x0`
8	`core0en`	core 0 clock enable	`RW`	`0x0`
7	`Reserved_5`	Reserved bitfield added by Magillem	`RO`	`0x1`
6	`s2fuser0clken`	Enables clock s2f_user0_clk output	`RW`	`0x0`
5	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
4	`csclken`	Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)	`RW`	`0x0`
3	`l4spclken`	Enables clock l4_sp_clk output	`RW`	`0x0`
2	`l4mpclken`	Enables clock l4_mp_clk output	`RW`	`0x0`
1	`l4mainclken`	Enables clock l4_main_clk output	`RW`	`0x0`
0	`Reserved_0`	Reserved bitfield added by Magillem	`RO`	`0x0`