nocdiv 

         Contains fields that control clock dividers for NoC Clocks.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D10024 0x10D10044

Size: 32

Offset: 0x20

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

cspdbgclk

RW 0x2

cstraceclk

RW 0x0

csclk

RW 0x0

Reserved_6

RO 0x0

mpuperiphdiv

RW 0x2

ccudiv

RW 0x1

softphydiv

RW 0x2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x1

l4spclk

RW 0x2

l4mpclk

RW 0x1

l4sysfreeclk

RW 0x2

Reserved_0

RO 0x0

nocdiv Fields

Bit Name Description Access Reset
31:30 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
29:28 cspdbgclk 
The external cs_pdbg_clk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
3 Divide By 8
RW 0x2
27:26 cstraceclk 
The external cs_trace_clk divider is specified in this field.  The cs_trace_clk is used by the actual trace interface to the debugger.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
3 Divide By 8
RW 0x0
25:24 csclk 
The external cs_at_clk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
3 Divide By 8
RW 0x0
23:22 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
21:20 mpuperiphdiv 
The external OCRAM and GIC-600 divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
RW 0x2
19:18 ccudiv 
The external ccu clk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
RW 0x1
17:16 softphydiv 
The external soft PHY divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
RW 0x2
15:8 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x1
7:6 l4spclk 
The external l4_sp_clk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
RW 0x2
5:4 l4mpclk 
The external l4_mp_clk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
RW 0x1
3:2 l4sysfreeclk 
The external l4sysfreeclk divider is specified in this field.
Value Description
0 Divide By 1
1 Divide By 2
2 Divide By 4
RW 0x2
1:0 Reserved_0 
Reserved bitfield added by Magillem
 RO 0x0