ssc
Spread Spectrum Clocking (SSC) Control and Status Registers.
| Module Instance | Base Address | Register Address |
|---|---|---|
i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000
|
0x10D10024
|
0x10D10074
|
Size: 32
Offset: 0x50
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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ssc Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:9 |
Reserved_2
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 8 |
stat
|
Indicates whether SSC is running. 1—SSC is active/enabled. Will only go to 1 once ictl_pll_freqgen_ssc_en_a has been asserted to 1. HP PLL output is at a SSC frequency. 0—SSC is disabled and that the HP PLL output frequency has returned to nominal frequency.
|
RO
|
0x0
|
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| 7:1 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 0 |
en
|
Enables/Disables SSC. 1—SSC is enabled (HP PLL output is running at spread spectrum mode) 0—SSC is disabled (HP PLL output will be at the nominal frequency)
|
RW
|
0x0
|