pllc2 

         Channel C2 frequency settings for the main PLL
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D10024 0x10D10064

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

stat

RO 0x0

mute

RW 0x0

en

RW 0x0

bypas

RW 0x0

Reserved_1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

div

RW 0x7

pllc2 Fields

Bit Name Description Access Reset
31:30 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
29 stat 
HP PLL state transition status for clk_slice_2.
1—Completed
0—In transition
Once state transition excluding disconnect state transition, for example power state, phase change and divider change transition, is requested, status will be de-asserted to indicate state transition is underway. 
Once the state transition is completed, status will be asserted.
Value Description
0 Transition
1 Completed
RO 0x0
28 mute 
Mutes PLL clock_slice_2 outputs without any glitch:
1—Output clocks are muted to 1’b0
0—Output clocks are active
HP PLL clock slice output will be automatically muted if the HP PLL IP is in PD, and in Ready state if HP PLL IP loses lock.
Value Description
0 Output_Clock_Slice_2_Active
1 Output_Clock_Slice_2_Muted
RW 0x0
27 en 
PLL channel 2 output enable; 
HP PLL clk_slice_2 enable control.
1—Enable
0—Disable
As long as one of the clock slices is enabled, the HP PLL IP will be powered up.
Value Description
0 DISABLE
1 ENABLE
RW 0x0
26 bypas 
PLL channel 2 output bypass. Before lock, it is muted, regardless of its value. 
After lock, if enabled (en==1) and bypass=1, this outputs refclk.
Value Description
0 UNBYPASS
1 BYPASS
RW 0x0
25:11 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
10:0 div 
The ock_pll_clkslice_2 divider ratio in binary code.
In source-synchronous mode, ictl_pll_clkslice_2_div_[10:0] can be dynamically updated when PLL is in Ready state or in PD state. In both cases, the change must happen synchronous to the rising
edge of ick_pll_ctrl. In asynchronous mode, it can only be updated in PD state. By default, this pin operates in source-synchronous mode.
(Can be dynamically updated after lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter glitches for 8'd1 and 8d'2 cases. )
RW 0x7