bypassr 

         Write One to Clear corresponding fields in Bypass Register.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D10024 0x10D10038

Size: 32

Offset: 0x14

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_6

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_6

RO 0x0

core3

RW 0x1

core2

RW 0x1

core01

RW 0x1

dsu

RW 0x1

Reserved_2

RO 0x1

s2fuser0

RW 0x1

noc

RW 0x1

Reserved_0

RO 0x1

bypassr Fields

Bit Name Description Access Reset
31:8 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
7 core3 
If set, the core3 clock will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
6 core2 
If set, the core2 clock will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
5 core01 
If set, the core01 clock will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
4 dsu 
If set, the DSU clock will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
3 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x1
2 s2fuser0 
If set, the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
1 noc 
If set, the NOC clock group will be bypassed to the input clock reference of the Main PLL.
 RW 0x1
0 Reserved_0 
Reserved bitfield added by Magillem
 RO 0x1