vcocalib 

         VCO calibration control registers.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D10024 0x10D10058

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

clr

RW 0x0

banksel

RW 0x0

Reserved_2

RO 0x0

mscnt

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x2

hscnt

RW 0x7C

vcocalib Fields

Bit Name Description Access Reset
31:28 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
27 clr 
HP PLL calibration clear control.
Assertion of this signal will clear the calibrated analog parameter values stored during cold-start in the calibration bank selected by ictl_pll_cfg_index_a_[1:0]. 
ln other words, this signal will trigger PLL to go through cold start sequence when exiting Power-Down (PD) state the next time the cleared calibration bank is selected. Assertion of this signal is only allowed when PLL is in PD state (all four clock slices are disabled). 
Status signal, octl_pll_clkslice*_status_a, will be de-asserted to indicate the clear request is acknowledged by the HP PLL IP. Users should de-assert ictl_pll_cal_clr_a and wait for assertion of status to indicate the clear event is completed.
RW 0x0
26:25 banksel 
Controls the calibration bank that will be used to store, restore or clear HP PLL calibration code.
0—Select calibration bank 0
1—Select calibration bank 1
2—Select calibration bank 2
3—Select calibration bank 3
 RW 0x0
24 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
23:16 mscnt 
ictl_pll_calvcomeascount_nt_[7:0] = 100/(Fvco/Fref_ effective_digital)

Where:
Fref_effective_digital = Fref/(2^ictl_pll_drefdiv_nt_[1:0])
This control can only be set while the HP PLL IP is in Reset or PD state. It cannot be switched dynamically.
0—Divided by 1
1—Divided by 2
2—Divided by 4
Note: The refclkdiv reqister is configured to the Membus interface. Default value is 1.
RW 0x1
15:10 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x2
9:0 hscnt 
VCO calibration parameter:
ictl_pll_calvcohscount_nt_[9:0] = (ictl_pll_mdiv_a_[9:0](At Reset)) * ictl_pll_calvcomeascount_nt_[7:0] * (2^ictl_pll_drefdiv_nt_[1:0])/ictl_pll_arefdiv_nt_[3:0][5:0] (At Reset)-4.
This control can be only set while the HP PLL IP is at Reset or PD state. It cannot be switched dynamically.
RW 0x7C