mainpllgrp Summary

Contains registers with settings for the Main PLL.

Base Address: 0x10D10024


Register Address Offset	Bit Fields
`i_clk_mgr__clkmgr_csr__10d10000__mainpllgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`
`en` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_9` `RO 0x0`				`core3en` `RW 0x1`	`core2en` `RW 0x1`	`core1en` `RW 0x1`	`core0en` `RW 0x1`	`Reserved_5` `RO 0x1`	`s2fuser0clken` `RW 0x1`	`Reserved_4` `RO 0x1`	`csclken` `RW 0x1`	`l4spclken` `RW 0x1`	`l4mpclken` `RW 0x1`	`l4mainclken` `RW 0x1`	`Reserved_0` `RO 0x1`
`ens` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_9` `RO 0x0`				`core3en` `RW 0x0`	`core2en` `RW 0x0`	`core1en` `RW 0x0`	`core0en` `RW 0x0`	`Reserved_5` `RO 0x1`	`s2fuser0clken` `RW 0x0`	`Reserved_4` `RO 0x0`	`csclken` `RW 0x0`	`l4spclken` `RW 0x0`	`l4mpclken` `RW 0x0`	`l4mainclken` `RW 0x0`	`Reserved_0` `RO 0x0`
`enr` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_9` `RO 0x0`				`core3en` `RW 0x0`	`core2en` `RW 0x0`	`core1en` `RW 0x0`	`core0en` `RW 0x0`	`Reserved_5` `RO 0x1`	`s2fuser0clken` `RW 0x0`	`Reserved_4` `RO 0x0`	`csclken` `RW 0x0`	`l4spclken` `RW 0x0`	`l4mpclken` `RW 0x0`	`l4mainclken` `RW 0x0`	`Reserved_0` `RO 0x0`
`bypass` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_6` `RO 0x0`								`core3` `RW 0x1`	`core2` `RW 0x1`	`core01` `RW 0x1`	`dsu` `RW 0x1`	`Reserved_2` `RO 0x1`	`s2fuser0` `RW 0x1`	`noc` `RW 0x1`	`Reserved_0` `RO 0x1`
`bypasss` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_6` `RO 0x0`								`core3` `RW 0x1`	`core2` `RW 0x1`	`core01` `RW 0x1`	`dsu` `RW 0x1`	`Reserved_2` `RO 0x1`	`s2fuser0` `RW 0x1`	`noc` `RW 0x1`	`Reserved_0` `RO 0x1`
`bypassr` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_6` `RO 0x0`								`core3` `RW 0x1`	`core2` `RW 0x1`	`core01` `RW 0x1`	`dsu` `RW 0x1`	`Reserved_2` `RO 0x1`	`s2fuser0` `RW 0x1`	`noc` `RW 0x1`	`Reserved_0` `RO 0x1`
`nocclk` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`nocdiv` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`		`cspdbgclk` `RW 0x2`		`cstraceclk` `RW 0x0`		`csclk` `RW 0x0`		`Reserved_6` `RO 0x0`		`mpuperiphdiv` `RW 0x2`		`ccudiv` `RW 0x1`		`softphydiv` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x1`								`l4spclk` `RW 0x2`		`l4mpclk` `RW 0x1`		`l4sysfreeclk` `RW 0x2`		`Reserved_0` `RO 0x0`
`pllglob` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_12` `RO 0x0`		`clr_lostlock_bypass` `RW 0x0`	`lostlock_bypass_en` `RW 0x1`	`modclkdiv` `RW 0x6`				`Reserved_9` `RO 0x0`		`fastrefclk` `RW 0x0`	`disctrl` `RW 0x0`	`clksync` `RW 0x0`	`pwrgatectrl` `RW 0x0`	`psrc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`		`drefclkdiv` `RW 0x0`		`arefclkdiv` `RW 0x1`				`Reserved_2` `RO 0x0`						`rst_n` `RW 0x0`	`pd_n` `RW 0x1`
`fdbck` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x2A`								`fdiv` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`fdiv` `RW 0x0`
`mem` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`					`err` `RO 0x0`	`wr` `RW 0x0`	`req` `RW 0x0`	`wdat` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`addr` `RW 0x0`
`memstat` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`rdata` `RO 0x0`
`vcocalib` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`				`clr` `RW 0x0`	`banksel` `RW 0x0`		`Reserved_2` `RO 0x0`	`mscnt` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x2`						`hscnt` `RW 0x7C`
`pllc0` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x5`
`pllc1` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x4`
`pllc2` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x7`
`pllc3` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`		`stat` `RO 0x0`	`mute` `RW 0x0`	`en` `RW 0x0`	`bypas` `RW 0x0`	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`div` `RW 0x8`
`pllm` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`						`mdiv` `RW 0x80`
`fhop` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`ack` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`req` `RW 0x0`	`Reserved_1` `RO 0x0`						`dir` `RW 0x0`
`ssc` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`stat` `RO 0x0`	`Reserved_1` `RO 0x0`							`en` `RW 0x0`
`lostlock` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`bypass_cleared` `RW 0x0`