DWC_usb31_block_dev Address Map

USB 3.1 Device Register Block
Module Instance Base Address End Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C700 0x1100CAFF
Register Group Offset
Rsvd_REGS 0
DEPCMDPAR2_REGS 0
DEV_IMOD_REGS 0
Register Offset Width Access Reset Value Description
DCFG 0x0 32 RW 0x00080805 
Device Configuration Register. 
  
  This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
DCTL 0x4 32 RW 0x00F00000 
Device Control Register
  
  Note:
  
  When Hibernation is not enabled using GCTL.GblHibernationEn field,
   - you can write any value to CSS, CRS, L1HibernationEn, and KeepConnect fields
   - L1HibernationEn, and KeepConnect fields always return 0 when read in this hibernation-disabled state
DEVTEN 0x8 32 RW 0x00000000 
Device Event Enable Register
   - This register controls the generation of device-specific events (see <link:ext>08_Descriptors.fm:event_buffer_content_devt,"Event Buffer Content for Device-Specific Events (DEVT)"</link> section in the Programming Guide). 
   - If an enable bit is set to 0, the event will not be generated.
DSTS 0xC 32 RW 0x00520004 
Device Status Register
  
  This register indicates the status of the device controller with respect to USB-related events.
  
  Note:
  
  When Hibernation is not enabled, RSS and SSS fields always return 0 when read.
DGCMDPAR 0x10 32 RW 0x00000000 
Device Generic Command Parameter Register
  
  This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register.
DGCMD 0x14 32 RW 0x00000000 
Device Generic Command Register
  
  This register enables software to program the controller using a single generic command interface to send link management packets and notifications. This register contains command, control, and status fields relevant to the current generic command, while the DGCMDPAR register provides the command parameter.
DCTL1 0x18 32 RW 0x00000000 
Device Control Register1.
  
  This register defines the control bits for the Device mode of operation.
DALEPENA 0x20 32 RW 0x00000000 
Device Active USB Endpoint Enable Register. 
  
  This register indicates whether a USB endpoint is active in a given configuration or interface.
DLDMENA 0x24 32 RW 0x00000000 
Device LDM Request Control Register.
  
  This register defines the control bits to enable the Device mode PTM (Precision Time Management defined as per the USB 3.1 Specification, Section 8.4.8) functionality by setting appropriate LDM request modes and controls.