DCTL1 

         Device Control Register1.
  
  This register defines the control bits for the Device mode of operation.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C700 0x1100C718

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_3

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_3

RW 0x0

EN_ENDXFER_ON_RJCT_STRM

RW 0x0

DIS_CLRSPR_SXFER

RW 0x0

reserved_0

RW 0x0

DCTL1 Fields

Bit Name Description Access Reset
31:3 reserved_31_3 
reserved_31_3
 RW 0x0
2 EN_ENDXFER_ON_RJCT_STRM 
EN_ENDXFER_ON_RJCT_STRM 
  
   Enable bit for new reject stream flow. On receiving a reject stream(FFFF) on USB side, Controller updates the application SW with STREAMEVT_NOTFOUND with streamid as FFFF, On decoding this event application SW needs to apply an ENDXFER command which flushes all FIFO's . 
  
   Until an ENDXFER is issued, Any stream packet received(on USB) will not lead to search of available streams in cache and release of ERDY.Controller writes STREAM_NOT_FOUND events until ENDXFER completion. 
   - 0: Feature disabled. No Reject status is updated to application SW.  
   - 1: Feature enabled, Reject staus is updated on receiving a reject stream(on USB).Decoding this event application SW needs to apply an ENDXFER.
  Note: By default, this bit is set to 0.
RW 0x0
1 DIS_CLRSPR_SXFER 
DIS_CLRSPR_SXFER
  
  Disable bit to clear intrenal SPR bit during start transfer. 
  
  If an End Transfer Command is issued during a transfer, there is a possibility that the internal SPR (short packet received/retry received) gets set, but not cleared. 
  
  The SPR clearing is now done when the new Start Transfer command is issued.
  
  Using this register bit, you can disable the clearing of the SPR bit during a Start Transfer command. 
   - 0: The SPR bit is cleared when a Start Transfer command is issued (default value).
   - 1: The SPR bit is not cleared when a Start Transfer command is issued. 
  Note: By default, this bit is set to 0.
RW 0x0
0 reserved_0 
reserved_0
 RW 0x0