DLDMENA 

         Device LDM Request Control Register.
  
  This register defines the control bits to enable the Device mode PTM (Precision Time Management defined as per the USB 3.1 Specification, Section 8.4.8) functionality by setting appropriate LDM request modes and controls.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C700 0x1100C724

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LDMADJ

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDMDUR

RW 0x0

NOLOWPWRDUR

RW 0x0

LDMRQS

RW 0x0

LDMENA

RW 0x0

DLDMENA Fields

Bit Name Description Access Reset
31:16 LDMADJ 
LDMADJ
  
  LDM request interval duration (LDMADJ)
  
  This field indicates Link Delay adjustment in terms of nano-seconds
  
  After receiving Link Delay through LDM events the application must set these bits with average value.
  
  After receiving ClearFeature(LDM_ENABLE) the application must program and reset these bits.
RW 0x0
15:8 LDMDUR 
LDMDUR
  
  LDM request interval duration (LDMDUR)
  
  This field indicates gap between two LDM request in terms of microframes
  
  After receiving SetFeature(LDM_ENABLE) the application must set these bits.
  
  After receiving ClearFeature(LDM_ENABLE) the application must program and reset these bits.
RW 0x0
7:4 NOLOWPWRDUR 
NOLOWPWRDUR
  
  No Low Power Duration (NOLOWPWRDUR)
  
  After starting a transfer on an ESS ISOC endpoint, the application must program these bits.
  
  Each count represents the duration in terms of 8 ms. For example, a value of 3 represents 24 ms.
RW 0x0
3:1 LDMRQS 
LDMRQS
  
  LDM number of requests (LDMRQS)
  
  This field indicates how many LDM requests Controller sends. A value of zero indicates request to send forever
  
  After receiving SetFeature(LDM_ENABLE) the application must set these bits.
  
  After receiving ClearFeature(LDM_ENABLE) the application must program and reset these bits.
RW 0x0
0 LDMENA 
LDMENA
  
  LDM enabled (LDMENA)
  
  This field indicates PTM protocol LDM request is enabled
  
  After receiving SetFeature(LDM_ENABLE) the application must set this bit.
  
  After receiving ClearFeature(LDM_ENABLE) the application must program and reset this bit.
  
  After receiving 4 consecutive timeout response to LDM, Hardware resets this bit.
RW 0x0