DSTS 

         Device Status Register
  
  This register indicates the status of the device controller with respect to USB-related events.
  
  Note:
  
  When Hibernation is not enabled, RSS and SSS fields always return 0 when read.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C700 0x1100C70C

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_30

RO 0x0

DCNRD

RO 0x0

SRE

RW 0x0

reserved_27_26

RO 0x0

RSS

RO 0x0

SSS

RO 0x0

COREIDLE

RO 0x0

DEVCTRLHLT

RO 0x1

USBLNKST

RO 0x0

RXFIFOEMPTY

RO 0x1

SOFFN

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOFFN

RO 0x0

CONNECTSPD

RO 0x4

DSTS Fields

Bit Name Description Access Reset
31:30 reserved_31_30 
Reserved_31_30
 RO 0x0
29 DCNRD 
Device Controller Not Ready 
  
  The bit indicates that the controller is in the process of completing the state transitions while entering or exiting hibernation. 
   - While entering hibernation, after the DCTL[31].Run/Stop is reset, this gives a window of about 2 to 7 MAC clock cycles plus the bus clock-to-MAC clock round trip synchronization delay to ensure that the correct link state is read by the software. Software must process DSTS.USBLnkSt when this bit goes 0.
   - While exiting hibernation, to complete the state transitions, it takes 256 bus clock cycles from the time DCTL[31].Run/Stop is set. During hibernation, if the UTMI/ULPI PHY is in suspended state, then the 256-bus clock cycle delay starts after the PHY exited suspended state. Software must set DCTL[31].Run/Stop to '1' and wait for this bit to be de-asserted to zero before processing DSTS.USBLnkSt. 
  
  This bit is valid only when DWC_USB31_EN_PWROPT is set to 2 and GCTL[1].GblHibernationEn =1.
RO 0x0
28 SRE 
Save Restore Error - currently not supported
  If an error occurs during a Save or Restore operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save or Restore operation is initiated or when written with '1'
 RW 0x0
27:26 reserved_27_26 
Reserved
 RO 0x0
25 RSS 
RSS Restore State Status   
  
  This bit is similar to the USBSTS.RSS in host mode.
  
  When the controller finishes the restore process, it completes the command by setting DSTS.RSS to '0'.
 RO 0x0
24 SSS 
SSS Save State Status  
  
  This bit is similar to the USBSTS.SSS in host mode.
  
  When the controller has finished the save process, it completes the command by setting DSTS.SSS to '0'.
 RO 0x0
23 COREIDLE 
Core Idle   
  
  The bit indicates that the controller finished transferring all RxFIFO data to system memory, writing out all completed descriptors, and all Event Counts are zero.
  
  Note: While testing for Reset values, mask out the read value. This bit represents the changing state of the controller and does not hold a static value.
 RO 0x0
22 DEVCTRLHLT 
Device Controller Halted 
  
  This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1.
  
  The controller sets this bit to 1 when, after software sets Run/Stop to 0, the controller is idle and the lower layer finishes the disconnect process.
  
  When Halted=1, the controller does not generate Device events. 
  
  Note: The controller does not set this bit to 1 if GEVNTCOUNTn has some valid value. Software needs to acknowledge the events that are generated (by writing to GEVNTCOUNTn) while it is waiting for this bit to be set to 1.
 RO 0x1
21:18 USBLNKST 
USBLNKST.
  
  USB/Link State
  
  In SS mode: LTSSM State
   - 4'h0: U0
   - 4'h1: U1
   - 4'h2: U2
   - 4'h3: U3
   - 4'h4: ESS_DIS
   - 4'h5: RX_DET
   - 4'h6: ESS_INACT
   - 4'h7: POLL
   - 4'h8: RECOV
   - 4'h9: HRESET
   - 4'ha: CMPLY
   - 4'hb: LPBK
   - 4'hf: Resume/Reset
  In HS/FS/LS mode:
   - 4'h0: On state
   - 4'h2: Sleep (L1) state
   - 4'h3: Suspend (L2) state
   - 4'h4: Disconnected state
   - 4'h5: Early Suspend state (valid only when Hibernation is disabled, GCTL[1].GblHibernationEn = 0)
   - 4'he: Reset (valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1)
   - 4'hf: Resume (valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1)
  The Resume/Reset link state indicates that the controller received a resume or USB reset request from the host while the link was in hibernation. Software must write '8' (Recovery) to the DCTL.ULStChngReq field to acknowledge the resume/reset request. 
  
  The Early Suspend link state is an early indication of device suspend in HS/FS. The link state changes to Early Suspend after detecting bus idle for 3ms.
   - In HS operation, this is an indication that the USB bus (that is, LineState) has been in idle (SE0) for 3ms. However, it does not confirm whether the next process is Suspend or Reset. The device checks the bus again after pull up enable delay and if the line state indicates Suspend (full speed J), then the device waits for additional time (~3ms) to indicate the actual Suspend state.
   - In FS operation, this is an indication that the USB bus (that is, LineState) has been in idle (J) for 3ms. The device waits for additional time (~3ms of Idle) to indicate the actual Suspend state.
  
  When Hibernation is enabled, GCTL[1].GblHibernationEn = 1, this field USBLnkSt is valid only when DSTS[29].DCNRD = 0.
 RO 0x0
17 RXFIFOEMPTY 
RxFIFO Empty.
 RO 0x1
16:3 SOFFN 
Frame/Microframe/ITP Number of the Received SOF. 
  
  When the controller is operating at SuperSpeed/SuperSpeedPlus, 
   - [16:3] indicates the microframe/ITP number
  When the controller is operating at high-speed, 
   - [16:6] indicates the frame number
   - [5:3] indicates the microframe number
  When the controller is operating at full-speed, 
   - [16:14] is not used. Software can ignore these 3 bits
   - [13:3] indicates the frame number
  Note: After power-on reset, the controller generates the microframe number internally for every 125us if the USB host has not issued SOF/ITP yet. During P3 state, the duration of SOFFN is based on the suspend_clk frequency.
 RO 0x0
2:0 CONNECTSPD 
Connected Speed (ConnectSpd)
  
  Indicates the speed at which the DWC_usb31 controller has come up after speed detection through an ESS speed negotiation or USB2.0 chirp sequence.
   - 3'b101: Enhanced SuperSpeed (USB 3.1 PHY clock is running at 156.25 or 312.5 MHz operating at 10Gbps)
   - 3'b100: SuperSpeed (PHY clock is running at 125 or 250 MHz operating at 5Gbps)
   - 3'b000: High-speed (PHY clock is running at 30 or 60 MHz)
   - 3'b001: Full-speed (PHY clock is running at 30 or 60 MHz)
  Low-speed is not supported for devices using a UTMI+ PHY.
Value Description
0x0 High-speed (PHY clock is running at 30 or 60 MHz)
0x1 Full-speed (PHY clock is running at 30 or 60 MHz)
0x4 SuperSpeed (PHY clock is running at 125 or 250 MHz)
0x5 Enhanced SuperSpeed (USB3.1 PHY clock is running at 156.25 or 312.5 MHz operating at 10Gbps)
RO 0x4