DCFG 

         Device Configuration Register. 
  
  This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C700 0x1100C700

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_25

RW 0x0

reserved_24

RW 0x0

IgnStrmPP

RW 0x0

LPMCAP

RW 0x0

NUMP

RW 0x4

INTRNUM

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTRNUM

RW 0x0

reserved_10_11

RW 0x0

DEVADDR

RW 0x0

DEVSPD

RW 0x5

DCFG Fields

Bit Name Description Access Reset
31:25 reserved_31_25 
Reserved_31_25
 RW 0x0
24 reserved_24 
Reserved
 RW 0x0
23 IgnStrmPP 
IgnoreStreamPP
  This bit only affects stream-capable bulk endpoints.
  
  When this bit is set to '0' and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints, or it receives an ACK with the NumP field set to 0 and PP set to 0 for IN endpoints, the controller attempts to search for another stream (CStream) to initiate to the host. However, there are two situations where this behavior is not optimal:
   - When the host is setting PP=0 even though it has not finished the stream, or
   - When the endpoint on the device is configured with one transfer resource and therefore does not have any other streams to initiate to the host.
  When this bit is set to '1', the controller ignores the Packet Pending bit for the purposes of stream selection and does not search for another stream when it receives DP(PP=0) or ACK(NumP=0, PP=0). This can enhance the performance when the device system bus bandwidth is low or the host responds to the ERDY transmission of the controller very quickly.
 RW 0x0
22 LPMCAP 
LPM Capable 
  
  The application uses this bit to control the DWC_usb31 controller LPM capabilities. If the controller operates as a non-LPM-capable device, it cannot respond to LPM transactions.
   - 1'b0: LPM capability is not enabled.
   - 1'b1: LPM capability is enabled.
 RW 0x0
21:17 NUMP 
Number of Receive Buffers. 
  
  This bit indicates the number of receive buffers to be reported in the ACK TP.
  
  The DWC_usb31 controller uses this field if GRXTHRCFG.USBRxPktCntSel is set to '0'. The application can program this value based on RxFIFO size, buffer sizes programmed in descriptors, and system latency.
  
  For an OUT endpoint, this field controls the number of receive buffers reported in the NumP field of the ACK TP transmitted by the controller.
  
  Note: This bit is used in host mode when Debug Capability is enabled.
 RW 0x4
16:12 INTRNUM 
Interrupt number 
  
  Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated.
 RW 0x0
11:10 reserved_10_11 
Reserved
 RW 0x0
9:3 DEVADDR 
Device Address.
  
  The application must perform the following:
   - Program this field after every SetAddress request.
   - Reset this field to zero after USB reset.
 RW 0x0
2:0 DEVSPD 
Device Speed. 
  
  Indicates the speed at which the application requires the controller to connect, or the maximum speed the application can support. 
  
  However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the controller is connected.
   - 3'b101: Enhanced SuperSpeed (USB 3.1 PHY clock is 156.25 MHz or 312.5 MHz operating at 10Gbps)
   - 3'b100: SuperSpeed (USB 3.1 PHY clock is 125 MHz or 250 MHz operating at 5Gbps)
   - 3'b000: High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
   - 3'b001: Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
Value Description
0x0 High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
0x1 Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
0x4 SuperSpeed (USB 3.1 PHY clock is 125 MHz or 250 MHz operating at 5Gbps)
0x5 Enhanced SuperSpeed (USB 3.1 PHY clock is 156.25 MHz or 312.5 MHz operating at 10Gbps)
RW 0x5