DWC_usb31_block_dev Summary

USB 3.1 Device Register Block

Base Address: 0x1100C700


Register Address Offset	Bit Fields
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_dev__SEG_L4_AHB_USB1_0x0_0x100000`
`DCFG` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_25` `RW 0x0`							`reserved_24` `RW 0x0`	`IgnStrmPP` `RW 0x0`	`LPMCAP` `RW 0x0`	`NUMP` `RW 0x4`					`INTRNUM` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`INTRNUM` `RW 0x0`				`reserved_10_11` `RW 0x0`		`DEVADDR` `RW 0x0`							`DEVSPD` `RW 0x5`
`DCTL` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RUN_STOP` `RW 0x0`	`CSFTRST` `RW 0x0`	`reserved_29` `RW 0x0`	`HIRDTHRES` `RW 0x0`					`LPM_NYET_thres` `RW 0xF`				`KeepConnect` `RW 0x0`	`L1HibernationEn` `RW 0x0`	`CRS` `RW 0x0`	`CSS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`reserved_15_13` `RO 0x0`			`INITU2ENA` `RW 0x0`	`ACCEPTU2ENA` `RW 0x0`	`INITU1ENA` `RW 0x0`	`ACCEPTU1ENA` `RW 0x0`	`ULSTCHNGREQ` `WO 0x0`				`TSTCTL` `RW 0x0`				`reserved_0` `RO 0x0`
`DEVTEN` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LDMEVTEN` `RW 0x0`	`L1WKUPEVTEN` `RW 0x0`	`reserved_13` `RO 0x0`	`VENDEVTSTRCVDEN` `RW 0x0`	`reserved_11` `RW 0x0`	`reserved_10` `RW 0x0`	`ERRTICERREVTEN` `RW 0x0`	`L1SUSPEN` `RW 0x0`	`SOFTEVTEN` `RW 0x0`	`U3L2L1SuspEn` `RW 0x0`	`HibernationReqEvtEn` `RW 0x0`	`WKUPEVTEN` `RW 0x0`	`ULSTCNGEN` `RW 0x0`	`CONNECTDONEEVTEN` `RW 0x0`	`USBRSTEVTEN` `RW 0x0`	`DISSCONNEVTEN` `RW 0x0`
`DSTS` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_30` `RO 0x0`		`DCNRD` `RO 0x0`	`SRE` `RW 0x0`	`reserved_27_26` `RO 0x0`		`RSS` `RO 0x0`	`SSS` `RO 0x0`	`COREIDLE` `RO 0x0`	`DEVCTRLHLT` `RO 0x1`	`USBLNKST` `RO 0x0`				`RXFIFOEMPTY` `RO 0x1`	`SOFFN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SOFFN` `RO 0x0`													`CONNECTSPD` `RO 0x4`
`DGCMDPAR` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PARAMETER` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PARAMETER` `RW 0x0`
`DGCMD` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CMDSTATUS` `RO 0x0`				`reserved_11` `RO 0x0`	`CMDACT` `RW 0x0`	`reserved_9` `RO 0x0`	`CMDIOC` `RW 0x0`	`CMDTYP` `RW 0x0`
`DCTL1` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`reserved_31_3` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`reserved_31_3` `RW 0x0`													`EN_ENDXFER_ON_RJCT_STRM` `RW 0x0`	`DIS_CLRSPR_SXFER` `RW 0x0`	`reserved_0` `RW 0x0`
`DALEPENA` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`USBACTEP` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`USBACTEP` `RW 0x0`
`DLDMENA` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LDMADJ` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LDMDUR` `RW 0x0`								`NOLOWPWRDUR` `RW 0x0`				`LDMRQS` `RW 0x0`			`LDMENA` `RW 0x0`