CQRS Address Map

Module Instance Base Address End Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x1080845F
Register Offset Width Access Reset Value Description
CQRS00 0x0 32 RO 0x00000510 
CQRS00 - Command Queuing Version
CQRS01 0x4 32 RO 0x00000000 
CQRS01 - Command Queuing Capabilities
CQRS02 0x8 32 RO 0x00000000 
CQRS02 - Command Queuing Configuration
CQRS03 0xC 32 RO 0x00000000 
CQRS03 - Command Queuing Control
CQRS04 0x10 32 RO 0x00000000 
            CQRS04 - Command Queuing Interrupt Status\n
            This register has several status bit related to specific interrupt event.
            When even happened and related Command Queuing Interrupt Status Enable is set, the status bit is set to 1.
            The bits can be cleared by S/W.\n
            Write 0 clears bit.\n
            Write 1 is ignored.
CQRS05 0x14 32 RO 0x00000000 
            CQRS05 - Command Queuing Interrupt Status Enable\n
            Statuses Enable bits enables interrupt sources. The status is enabled when bit is set 1 (S/W wrote 1 to the field).
CQRS06 0x18 32 RO 0x00000000 
            CQRS06 - Command Queuing Interrupt Signal Enable\n
            This register allows to turn on or turn off interrupt notification separately
            for each bit of the Command Queuing Interrupt Status.  When Interrupt status bit
            is set 1 and related field in this register is set (S/W wrote 1 to the filed),
            the Interrupt Status is reported on interrupt port.
CQRS07 0x1C 32 RW 0x00000000 
            CQRS07 - Interrupt Coalescing\n
            This register allows to group a CQ transfer and report single interrupt for entire group of requested tasks.
CQRS08 0x20 32 RW 0x00000000 
CQRS08 - Command Queuing Task Descriptor List Base Address
CQRS09 0x24 32 RW 0x00000000 
CQRS09 - Command Queuing Task Descriptor List Base Address Upper 32 Bits
CQRS10 0x28 32 RW 0x00000000 
            CQRS10 - Command Queuing Task Doorbell\n
            CQ has 32 tasks have individual bits to start operation on desired task.
            The S/W writes 1 on any position from 0 to 31 to start task 0 to 31.
            The S/W can request more than one task in single write.
            The CQ Engine process tasks in order they were requested:\n
            - when more than one task is requested in single register write, the task with
            lower number has higher priority over task with higher number\n
            - task(s) requested in earlier register write has higher priority over task(s)
            in later register write\n
            The order of the tasks are maintained during all phases of transaction. If given
            task is not ready for execution, the CQ Engine takes next task with highest
            number.\n
            CQ Engine needs several clock cycles to push requested in the single register
            write Task Doorbell to queue.  The slave interface ends write transfer as soon
            all tasks are in the queue.\n
            When S/W writes 0 to bit in this register, the related task won't start - this
            value is ignored.\n
            Task Doorbell bit remain 1 until task execution is completed, task is cleared by
            Clear All Task or Clear Task with this number or CQ Engine is disabled (CQE=0).
CQRS11 0x2C 32 RW 0x00000000 
            CQRS11 - Task Complete Notification\n
            32 bits related to 32 tasks. If task N is completed N bit is set 1.
            Bit that is set 1 can be cleared by writing 1 to this bit.
CQRS12 0x30 32 RO 0x00000000 
CQRS12 - Device Queue Status
CQRS13 0x34 32 RO 0x00000000 
            CQRS13 - Device Pending Tasks\n
            This register information which task is submitted to eMMC (CMD44 and CMD45 was sent)
            and is not executed. Task N is submitted and not executed when N bit is set 1.
            Bit N is cleared when task N is completed.
CQRS14 0x38 32 RW 0x00000000 
            CQRS14 - Task Clear\n
            S/W writes 1 to N bit of this register to clear task N.
            Bit remains 1 until clear operation is completed. Once operations ends, the CQE clears this bit to 0.
            The S/W has to ensure the CQ Engine is halted before clearing tasks.
            The S/W can clear only single task.  When any bit of this register is set, the
            S/W has no to request new task clear. This operation clears only task in the Host Controller.
            The S/W should take care about clearing task in the device.\n
            Writing 0 to register is ignored.
CQRS16 0x40 32 RO 0x00000000 
CQRS16 - Send Status Configuration 1
CQRS17 0x44 32 RO 0x00000000 
CQRS17 - Send Status Configuration 2
CQRS18 0x48 32 RO 0x00000000 
CQRS18 - Command Response for Direct-Command Task
CQRS20 0x50 32 RW 0x00000000 
CQRS20 - Response Mode Error Mask
CQRS21 0x54 32 RO 0x00000000 
CQRS21 - Task Error Information
CQRS22 0x58 32 RO 0x00000000 
CQRS22 - Command Response Index
CQRS23 0x5C 32 RO 0x00000000 
CQRS23 - Command Response Argument